L99SM81V datasheet(47/85 Pages) STMICROELECTRONICS

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L99SM81V

ST SPI protocol

DocID027599 Rev 4

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5.2

Protocol

5.2.1

SDI frame

The data-in frame consists of 24 bits (OpCode + Address + Data).

The first two transmitted bits (MSB, MSB-1) contain the Operation Code which represents

the instruction to be performed. The following 6 bits (MSB-2 to MSB-7) represent the

address on which the operation will be performed.

The subsequent 16 bits contain the payload data.

Figure 30: SDI frame

Table 22: Operation codes

OC1

OC0

Description

Write Operation

Read Operation

Read & Clear Operation

Read Device Information

The operation code is used to distinguish between different access modes to the registers

of the slave device.

A Write Operation will lead to a modification of the addressed data by the payload if a write

access is allowed (e.g. Control Register, valid data). Besides this a shift out of the content

(data present at Communication Start) of the registers is performed.

A Read Operation shifts out the data present in the addressed register at Communication

Start. The payload data will be ignored and internal data will not be modified. In this device

a Burst Read can be performed.

A Read & Clear operation will lead to a clear of the addressed status bits. The bits to be

cleared are defi

ned first by address and secondly by the payload bits set to ‘1’. Besides this

a shift out of the content (data present at Communication Start) of the registers is

performed.

Status registers which change status during communication could be cleared by

the current Read & Clear Operation and are neither reported in the current

communication nor in the following communications. To avoid a loss of any

reported status it is recommended to clear selectively the bits of the status

registers, coherently with what reported in previous communications.

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