L9679E datasheet(13/124 Pages) STMICROELECTRONICS

13 / 124 page

Figure 6. IC operating state diagram

SSM Reset

Configuration enabled

- CFG_SYS register

Testing enabled for:

-Deploy time

-HS/LS switch

Configuration enabled for:

-Deploy mask

-Deployment profiles

-RSU channels

Init State

Diag State

Safing State

SPI DIAG_STATE

SPI SAFING_STATE

GADG0603180820PS

5.3

Oscillators

The device integrates two trimmed oscillators, both of them with spread spectrum capability selectable via the

CLK_CNF register.

The main oscillator runs at 16 MHz typ and is used to provide clock to the internal synchronous logic.

The auxiliary oscillator runs at 7.5 MHz typ. and is used to monitor the main oscillator. In case the main oscillator

frequency is lower than the minimum threshold, this condition is detected by the frequency monitor circuit and

latched into the CLKFRERR flag in the FLTSR register. Eventually a POR would be issued.

5.4

Reset control

The device provides an input RESET pin, used to reset the internal logic to safe control system operation in case

of internal ECU failures, and a soft reset SPI command.

A low-level signal on this input pin longer than TFLT_RESET_N deglitch filter, or the soft reset SPI command

reception, will produce the following changes on the IC:

•

Clearing of all internal logic registers to the default state

•

IC operating state going back to the Init State (see Figure 6. IC operating state diagram)

•

Running diagnostics being disabled

•

RSU channels being switched off and their data registers being reset to default state

•

Running deployments being interrupted.

The RESET pin input circuitry implements a deglitch filter to reject spurious transitions on the signal.

Moreover, the device implements an internal power on reset (POR) producing the same changes at IC level as

the RESET pin. This POR is triggered by:

•

GDN loss

•

BG error

•

Internal supply error

L9679E

Oscillators

DS12485 - Rev 5

page 13/124

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