L9300 datasheet(28/182 Pages) STMICROELECTRONICS

28 / 182 page

Symbol

Parameter

Test condition

Min

Typ

Max

Unit

VDD3_SEL

ovs_b

Overshoot at VBATP

step

VBATP step from 5.5 V to 13 V during

10 µs, IVDD3 = 500 mA, CVDD3 = 5 µF,

Guaranteed by design

10%

VDD3_SEL

VDD3_SEL soft

Slope control

VDRAIN=VBATP = 13 V IVDD3 =

10 mA, CVDD3 = 4.7 µF

V/ms VDD3_SEL

Diagnostic

VDD3_UV

VDD3_SEL undervoltage

VDD3_SEL

typ * (9.1/10)

VDD3_SEL

typ * (9.6/10)

VDD3_SEL

VDD3_UV_ft

VDD3_SEL undervoltage

filter time

Guaranteed by scan

µs

VDD3_SEL

VDD3_OV

VDD3_SEL overvoltage

VDD3_SEL

typ * (11/10)

VDD3_SEL

typ * (11.8/10)

VDD3_SEL

VDD3_OV_ft

VDD3_SEL overvoltage

filter time

Guaranteed by scan

µs

VDD3_SEL

1. If VDRAIN is supplied by VDD1, the value of the optional filtering capacitor must be chosen taking into

account VDD1 current limitation value vs in-rush current during regulator power-up and supply transients.

8.3.3

VDD3 error handling

Table 11. VDD3 type errors

Type of error

Detection

condition

Action

Clear SPI flag

Restart condition

VDD3 under voltage

ON state

RES1, RES2 driven low. VDD3 UNDER VOLTAGE SPI

flag (6) latched in SERVFLT register

On read

Automatic after fault

disappears

VDD3 over voltage

ON state

RES1, RES2 driven low. VDD3 OVER VOLTAGE SPI

flag (8) latched in SERVFLT register

On read

Automatic after fault

disappears

8.4

VDD4

8.4.1

VDD4 functional description

VDD4 is a linear regulator that can work with an external N-channel FET. An external feedback resistor sets the

output voltage of the regulator.

To configure VDD4 to work as a linear regulator, the VDD4_SH pin has to be left floating; the configuration

(VDD4_SH connected to supply line or open) is latched after VDD1 has reached. VDD_st_en threshold to avoid

wrong configuration detection during battery ramp-up. When used in linear configuration the unused pins can be

left floating (alternatively VDD4_BTS can be shorted with VDD4S to the source of external FET). Echo of the

latched configuration is available in SPI registers.

Dedicated monitors are present on VDD4_SEL pin to detect VDD4 undervoltage and overvoltage conditions;

voltage monitors are not masked during the power-up phase.

L9300

VDD4

DS12258 - Rev 4

page 28/182

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