AM6546 datasheet(265/284 Pages) TI

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9.2.4 High Speed Differential Signal Routing Guidance

The High-Speed Interface Layout Guidelines provides guidance for successful routing of the high speed

differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and

spacing limits. TI supports only designs that follow the board design guidelines contained in the application

report.

9.2.5 System Power Supply Monitor Design Guidelines

The VDDA_VSYS_MON pin provides a way to monitor the system power supply and is not fail-safe, unless

implemented with the appropriate resistor voltage divider source. This pin should be sourced with a resistor

voltage divider that receives its power from the system power supply.

The output of the resistor voltage divider is connected to the VDDA_VSYS_MON pin which has a trigger voltage

of 0.5 V ± 5%. The resistor voltage divider should be implemented such that it has a reference current in the

range of 1 µA to 50 µA, output voltage that never exceeds the maximum value defined in Section 7.1, Absolute

Maximums Ratings, and output voltage of 0.54 V when the system supply drops to its lowest desired operating

voltage.

The recommended output voltage of 0.54 V provides 40 mV of margin that includes 5% for tolerance of the

voltage monitor, 1% for tolerance of each resistor, plus 5 mV of potential error introduced by input leakage

current. This value ensures the voltage monitor will never trigger before reaching the expected trigger voltage.

Figure 9-5 presents an example, when the system power supply voltage is nominally 5 V and the desired trigger

threshold is -10% or 4.5 V.

Device

VDDA_VSYS_MON

SPRSP08_VSYS_MON_01

VSS

30 k

Ω

220 k

Ω

VSYS

(System Power Suplpy)

Figure 9-5. System Supply Monitor Voltage Divider Circuit

In this example the voltage divider ratio should be (4.5 V / 0.54 V) = 8.33 V. This ratio produces a 0.54 V

potential on the VDDA_VSYS_MON pin when the system power supply is 4.5 V. In this case, the voltage

monitor will trigger in the range of 3.88 V to 4.5 V. Precision 1% resistors with similar thermal coefficient are

recommended for implementing the resistor voltage divider.

9.2.6 MMC Design Guidelines

The MMC peripheral on this device contains an integrated SDIO LDO for handling automatic voltage transitions

for SD Interfaces. For details about how to connect the device pins associated with the SDIO LDO, refer to

Figure 9-10 through Figure 9-12.

9.2.7 Integrated Power Management Features

The device offers integrated power management features that simplify design and cost/BOM of the system level

power solution. Simplicity of the system design enables modular and scalable solutions suitable for platform

design and re-use. The AM65x Power Management Features User Guide introduces the integrated power

management features and advantages for system level power solution.

www.ti.com

AM6548, AM6528, AM6546, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

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Product Folder Links: AM6548 AM6528 AM6546 AM6526

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