AM6546 datasheet(202/284 Pages) TI

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Note

Philips I2C specification rise/fall timings apply only to MCU_I2C0 and WKUP_I2C0. MAIN_I2C[0:3]

use standard LVCMOS buffers to emulate open-drain buffers, and their rise/fall times should be

referenced using the device IBIS model.

Note

I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current

when the device is powered down.

For more details about features and additional description information on the device Inter-Integrated Circuit, see

the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.

7.9.5.13 MCAN

For more details about features and additional description information on the device Controller Area Network

Interface, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed

Description.

Table 7-41 presents timing conditions for MCANi interface. Table 7-42 presents timing parameters for MCANi

Interface.

Table 7-41. MCAN Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

V/ns

OUTPUT CONDITIONS

Output load capacitance

Table 7-42. MCAN Register to Pin Timings

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

tp(MCANi_TX)

Delay Time Max, Transmit Shift Register to MCANi_TX pin

tp(MCANi_RX)

Delay Time Max, MCANi_RX pin to receive shift register

For more information, see section Controller Area Network (MCAN) in the device TRM.

7.9.5.14 MCASP

For more details about features and additional description information on the device Multichannel Audio Serial

Port, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.

Table 7-43 presents timing conditions for MCASP0 to MCASP2.

Section 7.9.5.14.1 present timing requirements and switching characteristics for MCASP0 to MCASP2.

Table 7-43. MCASP Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.7

V/ns

OUTPUT CONDITIONS

Output load capacitance

PCB CONNECTIVITY REQUIREMENTS

td(Trace Delay)

Propagation delay of each trace

140

1080

td(Trace Mismatch Delay)

Propagation delay mismatch across all traces

100

AM6548, AM6528, AM6546, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

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