2

SY89832U

Micrel, Inc.

M9999-092005

hbwhelp@micrel.com or (408) 955-1690

September 2005

IN

/IN

EN

Q

/Q

0

110

1

1

011

0

XX

0

Note 1.

On next negative transition of the input signal (IN).

TRUTH TABLE

PACKAGE/ORDERING INFORMATION

Package

Operating

Package

Lead

Part Number

Type

Range

Marking

Finish

SY89832UMI

MLF-16

Industrial

832U

Sn-Pb

MLF-16

Industrial

832U

Sn-Pb

MLF-16

Industrial

832U with Pb-Free

NiPdAu

bar line indicator

Pb-Free

MLF-16

Industrial

832U with Pb-Free

NiPdAu

bar line indicator

Pb-Free

Notes:

1. Contact factory for die availability. Dice are guaranteed at T

2. Tape and Reel.

3. Pb-Free package is recommended for new designs.

Pin Number

Pin Name

Pin Function

15, 16

Q0, /Q0

LVDS Differential (Outputs): Normally terminated with 100

Ω across the pair (Q, /Q). See “LVDS

1, 2

Q1, /Q1

Outputs” section, Figure 2a. Unused outputs should be terminated with a 100

Ω resistor across

3, 4

Q2, /Q2

each pair.

5, 6

Q3, /Q3

8

EN

This single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The

synchronous enable ensures that enable/disable will only occur when the outputs are in a logic

LOW state. Note that this input is internally connected to a 25k

Ω pull-up resistor and will default

to logic HIGH state (enabled) if left open.

9, 12

/IN, IN

Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs

accept AC- or DC-Coupled differential signs as small as 100mV. Each pin of a pair internally

terminates to a VT pin through 50

Ω. Note that these inputs will default to an intermediate state if

left open. Pleae refer to the “Input Interface Applications” section for more details.

10

VREF–AC

Reference Voltage: These outputs bias to V

inputs (IN, /IN). For AC-Coupled applications, connect VREF-AC to VT pin and bypass with

0.01

µF low ESR capacitor to V

Maximum sink/source current is

±1.5mA. Due to the limited drive capability, each VREF-AC pin

is only intended to drive its respective VT pin.

11

VT

Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The

VT pins provide a center-tap to a termination network for maximum interface flexibility. See “Input

Interface Applications” section for more detaiils.

13

GND

Ground. GND pins and exposed pad must be connected to the most negative potential of the

device ground.

7, 14

VCC

Positive Power Supply: Bypass with 0.1

µF//0.01µF low ESR capacitors and place as close to

each VCC pin as possible.

PIN DESCRIPTION

13

14

15

16

12

11

10

9

1

2

3

4

8

7

6

5

Q1

/Q1

Q2

/Q2

IN

VT

VREF-AC

/IN

16-Pin MLF™ (MLF-16)