CD54ACT109, CD74ACT109

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SCHS327 – JANUARY 2003

3

POST OFFICE BOX 655303

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

TA = 25°C

–55

°C to

125

°C

–40

°C to

85

°C

UNIT

CC

MIN

MAX

MIN

MAX

MIN

MAX

IOH = –50 µA

4.5 V

4.4

4.4

4.4

VOH

VI =VIH or VIL

IOH = –24 mA

4.5 V

3.94

3.7

3.8

V

VOH

VI = VIH or VIL

IOH = –50 mA†

5.5 V

3.85

V

IOH = –75 mA†

5.5 V

3.85

IOL = 50 µA

4.5 V

0.1

0.1

0.1

VOL

VI =VIH or VIL

IOL = 24 mA

4.5 V

0.36

0.5

0.44

V

VOL

VI = VIH or VIL

IOL = 50 mA†

5.5 V

1.65

V

IOL = 75 mA†

5.5 V

1.65

II

VI = VCC or GND

5.5 V

±0.1

±1

±1

µA

ICC

VI = VCC or GND,

IO = 0

5.5 V

4

80

40

µA

DICC‡

VI = VCC – 2.1 V

4.5 V to

5.5 V

2.4

3

2.8

mA

Ci

10

10

10

pF

† Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize

power dissipation. Test verifies a minimum 50-

Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.

‡ Additional quiescent supply current per input pin, TTL inputs high, 1 unit load

ACT INPUT LOAD TABLE

INPUT

UNIT LOAD

J or CLK

1

K

0.53

CLR or PRE

0.58

Unit Load is

∆ICC limit specified in

electrical

characteristics

table

(e.g., 2.4 mA at 25

°C).

timing requirements over recommended operating conditions (unless otherwise noted)

–55

°C to

125

°C

–40

°C to

85

°C

UNIT

MIN

MAX

MIN

MAX

fclock

Clock frequency

100

114

MHz

t

Pulse duration

CLK high or low

5

4.4

ns

tw

Pulse duration

CLR or PRE low

5.5

4.8

ns

tsu

Setup time, before CLK

↑

J or K

5.5

4.8

ns

th

Hold time, after CLK

↑

J or K

0

0

ns

trec

Recovery time, before CLK

↑

CLR

↑ or PRE↑

2.5

2.2

ns