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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HT95C20P датащи(PDF) 15 Page - Holtek Semiconductor Inc |
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HT95C20P датащи(HTML) 15 Page - Holtek Semiconductor Inc |
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15 / 51 page  HT95CXXX Rev. 1.50 15 May 26, 2005 If the stack is full, any other interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. If immediate ser- vice is desired, the stack must be prevented from be- coming full. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro- gram memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the con- tents should be saved in advance. External interrupt is triggered by a high to low transition of the INT/TMR1 pin and the interrupt request flag EIF will be set. When the external interrupt is enabled, the stack is not full and the external interrupt is active, a sub- routine call to location 04H will occur. The interrupt re- quest flag EIF and EMI bits will be cleared to disable other interrupts. The Timer/Event Counter 0 interrupt is generated by a timeout overflow and the interrupt request flag T0F will be set. When the Timer/Event Counter 0 interrupt is en- abled, the stack is not full and the T0F bit is set, a sub- routine call to location 08H will occur. The interrupt request flag T0F and EMI bits will be cleared to disable further interrupts. The Timer/Event Counter 1 interrupt is generated by a timeout overflow and the interrupt request flag T1F will be set. When the Timer/Event Counter 1 interrupt is en- abled, the stack is not full and the T1F bit is set, a sub- routine call to location 0CH will occur. The interrupt request flag T1F and EMI bits will be cleared to disable further interrupts. The peripheral interrupt is activated when the FSK de- coder detect the ring signal or line reversal or FSK car- rier signal or FSK packet data. When these interrupts occurred, the interrupt request flag PERF will be set. When the peripheral interrupt is enabled, the stack is not full and the PERF is set, a subroutine call to location 10H will occur. The interrupt request flag PERF and EMI bits will be cleared to disable other interrupts. The real time clock interrupt is generated by a 1Hz RTC generator. When the RTC time-out occurs, the interrupt request flag RTCF will be set. When the RTC interrupt is enabled, the stack is not full and the RTCF is set, a sub- routine call to location 14H will occur. The interrupt re- quest flag RTCF and EMI bits will be cleared to disable other interrupts. The dialer I/O interrupt is triggered by any edge transi- tion onto HKS pin or a falling edge transition onto HDI pin or a rising edge transition onto HFI pin, the interrupt request flag DRF will be set. When the dialer I/O inter- rupt is enabled, the stack is not full and the DRF is set, a subroutine call to location 18H will occur. The interrupt request flag DRF and EMI bits will be cleared to disable other interrupts. Bit No. Label R/W Function 0 EMI RW Controls the master (global) interrupt (1=enabled; 0=disabled) 1 EEI RW Controls the external interrupt (1=enabled; 0=disabled) 2 ET0I RW Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled) 3 ET1I RW Controls the Timer/Event Counter1 interrupt (1=enabled; 0=disabled) 4 EIF RW External interrupt request flag (1=active; 0=inactive) 5 T0F RW Timer/Event Counter 0 request flag (1=active; 0=inactive) 6 T1F RW Timer/Event Counter1 request flag (1=active; 0=inactive) 7 ¾ RO Unused bit, read as ²0² INTC0 (0BH) Register Bit No. Label R/W Function 0 EPERI RW Control the peripheral interrupt (1=enable; 0=disable) 1 ERTCI RW Control the real time clock interrupt (1=enable; 0=disable) 2 EDRI RW Control the dialer I/O interrupt (1=enable; 0=disable) 3 ¾ RO Unused bit, read as ²0² 4 PERF RW Peripheral interrupt request flag (1=active; 0=inactive) 5 RTCF RW Internal real time clock interrupt request flag (1=active; 0=inactive) 6 DRF RW Internal dialer I/O interrupt request flag (1=active: 0=inactive) 7 ¾ RO Unused bit, read as ²0² INTC1 (1EH) Register |
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