HT86070 datasheet(13/25 Pages) HOLTEK

13 / 25 page

HT86030/HT86070

Rev. 1.00

February 20, 2006

During the execution of an interrupt subroutine, other in-

terrupt acknowledges are held until the RETI instruction

is executed or the EMI bit and the related interrupt con-

trol bit are set to 1 (of course, if the stack is not full). To

return from the interrupt subroutine, the RET or RETI in-

struction may be invoked. RETI will set the EMI bit to en-

able an interrupt service, but RET will not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests,

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

The Timer/Event Counter 0/1 interrupt request flag

(T0F/T1F) which enables Timer/Event Counter 0/1 con-

trol bit (ET0I/ET1I), the Timer Counter 3 interrupt re-

quest flag (T3F) which enables Timer Counter 3 control

bit (ET3I), and external interrupt request flag (EIF)

which enables external interrupt control bit (EEI) form

the interrupt control register (INTC:0BH and

INTCH:1EH). EMI, EEI, ET0I, ET1I and ET3I are used

to control the enabling/disabling of interrupts. These bits

prevent the requested interrupt begin serviced. Once

the interrupt request flags (T0F, T1F, T3F, EIF) are set,

they will remain in the INTC/INTCH register until the in-

terrupts are serviced or cleared by a software instruc-

tion.

It is recommended that application programs do not use

CALL subroutines within an interrupt subroutine. Inter-

rupts often occur in an unpredictable manner or need to

be serviced immediately in some applications. If only

one stack is left and the interrupt enable is not well con-

trolled, once a CALL subroutine if used in the interrupt

subroutine will corrupt the original control sequence.

Bit No. Label

Function

EMI

Controls the master (global) interrupt

(1= enabled; 0= disabled)

EEI

Controls the external interrupt

(1= enabled; 0= disabled)

ET0I

Controls the timer 0 interrupt

(1= enabled; 0= disabled)

ET1I

Controls the timer 1 interrupt

(1= enabled; 0= disabled)

EIF

External interrupt request flag

(1= active; 0= inactive)

T0F

Timer 0 request flag

(1= active; 0= inactive)

T1F

Timer 1 request flag

(1= active; 0= inactive)

Unused bit, read as

²0²

INTC (0BH) Register

Bit No.

Label

Function

0, 2~4, 6~7

Unused bit, read as

²0²

ET3I

Controls the timer 3 interrupt

(1= enabled; 0= disabled)

T3F

Timer 3 interrupt request flag

(1= active; 0= inactive)

INTCH (1EH) 1 Register

Interrupt Source

Priority

Vector

External Interrupt

04H

Timer/Event Counter 0 Overflow

08H

Timer/Event Counter 1 Overflow

0CH

Timer Counter 3 Overflow

14H

Oscillator Configuration

The HT86030/HT86070 provides two types of oscillator

circuit for the system clock, i.e., RC oscillator and crystal

oscillator. No matter what type of oscillator, the signal is

used for the system clock. The HALT mode stops the

system oscillator and ignores external signal to con-

serve power. If the RC oscillator is used, an external re-

sistor between OSC1 and VSS is required, and the

range of the resistance should be from 30k

W to 680kW.

The system clock, divided by 4, is available on OSC2

with pull-high resistor, which can be used to synchronize

external logic. The RC oscillator provides the most cost

effective solution. However, the frequency of the oscilla-

tion may vary with VDD, temperature, and the chip itself

due to process variations. It is therefore not suitable for

timing sensitive operations where accurate oscillator

frequency is desired.

On the other hand, if the crystal oscillator is selected, a

crystal across OSC1 and OSC2 is needed to provide the

feedback and phase shift required for the oscillator, and

no other external components are required. A resonator

may be connected between OSC1 and OSC2 to replace

the crystal and to get a frequency reference, but two ex-

ternal capacitors in OSC1 and OSC2 are required.

C r y s t a l O s c i l l a t o r

R C O s c i l l a t o r

O S C 1

O S C 2

f S Y S / 4

O S C 1

V D D

System Oscillator

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