Block

Description

Static Icon Control Circuit

This module generates the LCD waveform of the 4 annunciators and IBP signal. The

four independent static icons are enabled by software command. Icon signals are also

controlled by oscillator circuit, too.

LCD Driving Voltage

Generator

This module generates the LCD voltage needed for display output. It takes a single sup-

ply input and generates necessary bias voltages. It consists of:

To generate the VCCA1 voltage. Either doubler or tripler can be enabled.

Feedback gain control for initial LCD voltage. It can also be used with external contrast

control.

Divide the LCD display voltage (VLL2~VLL6) from the regulator output. This is low

power consumption circuit, which can save the most display current compare with tra-

ditional resistor ladder method.

Software control of 1/5 and 1/7 bias ratios to match the characteristic of LCD panel.

Provide 4 different compensation grade selections to satisfy the various liquid crystal

temperature grades. The grading can be selected by software control.

Software control of 16 voltage levels of LCD voltage.

By adjusting the gain control resistors connected externally, the contrast can be var-

ied.

All blocks can be individually turned off if external voltage generator is employed.

120 Bit Latch/33 Bit Latch

153 bit long registers, which carry the display signal information. First 33 bits are Com-

mon driving signals and other 120 bits are Segment driving signals. Data will be input to

the HV-buffer Cell for bumping up to the required level.

Level Selector

Level selector is a control of the display synchronization. Display voltage can be sepa-

rated into two sets and used with different cycles. Synchronization is important since it

selects the required LCD voltage level to the HV Buffer Cell for output signal voltage

pump.

HV Buffer Cell

(Level Shifter)

HV Buffer Cell works as a level shifter that translates the low voltage output signal to the

required driving voltage. The output is shifted out with an internal FRM clock, which co-

mes from the Display Timing Generator. The voltage levels are given by the level selec-

tor which is synchronized with the internal M signal.

HT0610

Rev. 1.00

3

February 24, 2004