HT82K94A datasheet(10/44 Pages) HOLTEK

10 / 44 page

HT82K94E/HT82K94A

Rev. 1.00

November 22, 2005

In addition, on entering the interrupt sequence or exe-

cuting the subroutine call, the status register will not be

pushed onto the stack automatically. If the contents of

the status are important and if the subroutine can cor-

rupt the status register, precautions must be taken to

save it properly.

Interrupt

The device provides an external interrupt and internal

timer/event counter and USB interrupts. The Interrupt

Control Register (INTC;0BH) contains the interrupt con-

trol bits to set the enable/disable and the interrupt re-

quest flags.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may occur during this interval but only

the interrupt request flag is recorded. If a certain inter-

rupt requires servicing within the service routine, the

EMI bit and the corresponding bit of the INTC may be set

to allow interrupt nesting. If the stack is full, the interrupt

request will not be acknowledged, even if the related in-

terrupt is enabled, until the SP is decremented. If immedi-

ate service is desired, the stack must be prevented from

becoming full.

All these kinds of interrupts except external interrupt

PA4/EXT have a wake-up capability. As an interrupt is

serviced, a control transfer occurs by pushing the pro-

gram counter onto the stack, followed by a branch to a

subroutine at specified location in the program memory.

Only the program counter is pushed onto the stack. If

the contents of the register or status register (STATUS)

are altered by the interrupt service program which cor-

rupts the desired control sequence, the contents should

be saved in advance.

The external and USB interrupt use the same vector lo-

cation (04H). There are EXTIF bit in USR register to indi-

cate whether this interrupt is external interrupt or not.

Also bit EXT-INTEN in SCC register is configured the

external interrupt is enable or disable.

USB interrupts are triggered by the following USB

events and the related interrupt request flag (USBF; bit

4 of the INTC) will be set.

· The corresponding USB FIFO is accessed from the

· The USB suspends signal from the PC

· The USB resumes signal from the PC

· The USB sends Reset signal

When the interrupt is enabled, the stack is not full and

the external interrupt is active, a subroutine call to loca-

tion 04H will occur. The interrupt request flag (USBF)

and EMI bits will be cleared to disable other interrupts.

When the PC Host access the FIFO of the HT82K94E/

HT82K94A, the corresponding request bit of the USR is

set, and a USB interrupt is triggered. So user can easily

decide which FIFO is accessed. When the interrupt has

been served, the corresponding bit should be cleared by

firmware. When the HT82K94E/HT82K94A receives a

USB Suspend signal from the Host PC, the suspend line

(bit0 of the USC) of the HT82K94E/HT82K94A is set

and a USB interrupt is also triggered.

Also when the HT82K94E/HT82K94A receives a Re-

sume signal from the Host PC, the resume line (bit3 of

the USC) of HT82K94E/HT82K94A is set and a USB in-

terrupt is triggered.

Whenever a USB reset signal is detected, the USB in-

terrupt is triggered.

The internal Timer/Event Counter 0 interrupt is initial-

ized by setting the Timer/Event Counter 0 interrupt re-

quest flag (; bit 5 of INTC), caused by a timer 0 overflow.

When the interrupt is enabled, the stack is not full and

the T0F bit is set, a subroutine call to location 08H will

occur. The related interrupt request flag (T0F) will be re-

set and the EMI bit cleared to disable further interrupts.

The internal Timer/Even Counter 1 interrupt is initialized

by setting the Timer/Event Counter 1 interrupt request

flag (;bit 6 of INTC), caused by a timer 1 overflow. When

the interrupt is enabled, the stack is not full and the T1F

is set, a subroutine call to location 0CH will occur. The

related interrupt request flag (T1F) will be reset and the

EMI bit cleared to disable further interrupts.

Bit No.

Label

Function

EMI

Controls the master (global) interrupt (1= enabled; 0= disabled)

EUI

Controls the USB interrupt (1= enabled; 0= disabled)

ET0I

Controls the Timer/Event Counter 0 interrupt (1= enabled; 0= disabled)

ET1I

Controls the Timer/Event Counter 1 interrupt (1= enabled; 0= disabled)

USBF

USB interrupt request flag (1= active; 0= inactive)

T0F

Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)

T1F

Internal Timer/Event Counter 1 request flag (1= active; 0= inactive)

Unused bit, read as

²0²

INTC (0BH) Register

HT82K94A датащи(PDF) 10 Page - Holtek Semiconductor Inc

HT82K94A датащи(HTML) 10 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

датащи скачать

ссылки URL