8019AS.doc
2001-05-10
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SPECIFICATION
RTL8019AS
7
31
SMEMRB
I
Host memory read command.
32
SMEMWB
I
Host memory write command. This pin is added to decode the
write command of a flash memory.
4.3. Memory Interface Pins (including BROM, EEPROM)
No.
Name
Type
Description
75
BCSB
O
BROM chip select. Active low signal, asserted when
BROM is read. RTL8019AS drives this pin low when
SA19-14 matches the selected BROM memory base
address and either of the 2 conditions below meets:
(1) SMEMRB is low
(2) SMEMWB is low and RTL8019AS's flash memory
write function is enabled.
76
EECS
O
9346 chip select. Active high signal, asserted when 9346
is read/write.
66-69, 71-74
BA21-14
O
BROM address.
77-82, 84-85
BD7-0
I/O
BROM data bus.
[79]
[EESK]
O
9346 serial data clock
[78]
[EEDI]
O
9346 serial data input
[77]
[EEDO]
I
9346 serial data output
The following pins are defined for jumper options. Their
states are latched at the falling edge of RSTDRV, then
they are changed to serve as the SRAM bus. Each of
them is internally pulled down by a 100KW resistor.
Therefore, the input will be low
when left open and
high when pulled up by a 10K resistor externally.
[66]
[PNP]
I
When it is high in jumperless mode (i.e. JP=low), the
RTL8019AS is forced into Plug and Play mode
regardless of the contents of 9346.
The following pins are don't care in jumperless mode
(JP=low).
[72-71, 69-67]
[BS4-0]
I
Select BROM size and base address.
[85-84, 82-81]
[IOS3-0]
I
Select I/O base address.
[77, 74]
[PL1-0]
I
Select network medium type.
[80-78]
[IRQS2-0]
I
Select one interrupt line among INT7-0.
65
JP
I
When high, this pin selects jumper mode. When low, it
selects jumperless modes (including RT jumperless and
Plug and Play).
After RTL8019AS latches all jumper status upon power on reset, these pins always* reflect the value of BPAGE
register directly in BROM page mode. In normal mode, BA16-21 are not used and BA14-15 act as:
BROM Size
BA14
BA15
16K
high
high
32K
SA14
high
64K
SA14
SA15
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