HT46R71D datasheet(9/46 Pages) HOLTEK

9 / 46 page

HT46R71D

Rev. 1.00

January 9, 2006

Data Memory

- RAM

The data memory (RAM) is designed with 57

´8 bits, and

is divided into two functional groups, namely; special

function registers 25

´8 bit and general purpose data

memory, 32

´8 bit most of which are readable/writable,

although some are read only. The special function regis-

ter are overlapped in any banks.

Of the two types of functional groups, the special func-

tion registers consist of an Indirect addressing register 0

(00H), a Memory pointer register 0 (MP0;01H), an Indi-

rect addressing register 1 (02H), a Memory pointer reg-

ister 1 (MP1;03H), a Bank pointer (BP;04H), an

Accumulator (ACC;05H), a Program counter lower-or-

der byte

(TBLP;07H), a Table higher-order byte register

(TBLH;08H), a Status register (STATUS;0AH), an Inter-

rupt control register 0 (INTC0;0BH), a Timer/Event

Counter 0 (TMR0; 0DH), a Timer/Event Counter 0 con-

trol register (TMR0C;0EH), a Timer/Event Counter 1

(TMR1H:0FH;TMR1L:10H), a Timer/Event Counter 1

control register (TMR1C;11H), I/O registers (PA;12H,

PB;14H) and I/O control registers (PAC;13H,

PBC;15H), an ADC control register (ADCR;18H), an

ADC chopper divider register (ADCD;1AH), an Interrupt

control register 1 (INTC1;1EH) and Charge Pump &

Regulator Control Register (CHPRC;1FH).

The remaining space before the 20H is reserved for fu-

ture expanded usage and reading these locations will

get

²00H². The general purpose data memory, ad-

dressed from 20H to 3FH , is used for data and control

information under instruction commands. All of the data

memory areas can handle arithmetic, logic, increment,

decrement and rotate operations directly. Except for

some dedicated bits, each bit in the data memory can be

set and reset by

²SET [m].i² and ²CLR [m].i². They are

also indirectly accessible through memory pointer regis-

ters (MP0;01H or MP1:03H).

After first setting up BP to the value of

²01H² to access

Bank 1 , these banks must then be accessed indirectly

using the Memory Pointer MP1. With BP set to a value

²01H², using MP1 to indirectly read or write to the

data memory areas with addresses from 20H~3FH will

result in operations to Bank 1. Directly addressing the

Data Memory will always result in Bank 0 being ac-

cessed irrespective of the value of BP.

Indirect Addressing Register

Location 00H and 02H are indirect addressing registers

that are not physically implemented. Any read/write op-

eration of [00H] and [02H] accesses the RAM pointed to

by MP0 (01H) and MP1 (03H) respectively. Reading lo-

cation 00H or 02H indirectly returns the result 00H.

While, writing it indirectly leads to no operation. The

memory pointer register (MP0, MP1) are 7-bit registers.

The function of data movement between two indirect ad-

dressing registers is not supported. The memory pointer

registers, MP0 and MP1, are both 7-bit registers used to

access the RAM by combining corresponding indirect

addressing registers. MP0 can only be applied to data

memory, while MP1 can be applied to data memory and

LCD display memory.

Accumulator

- ACC

The accumulator (ACC) is related to the ALU opera-

tions. It is also mapped to location 05H of the RAM and

is capable of operating with immediate data. The data

movement between two data memory locations must

pass through the ACC.

S p e c i a l P u r p o s e

D a t a M e m o r y

0 0 H

0 1 H

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H

1 E H

1 F H

G e n e r a l P u r p o s e

D a t a M e m o r y

( 3 2 B y t e s )

3 F H

2 0 H

I n d i r e c t A d d r e s s i n g R e g i s t e r 0

M P 0

I n d i r e c t A d d r e s s i n g R e g i s t e r 1

M P 1

B P

A C C

P C L

T B L P

T B L H

M O D E

S T A T U S

I N T C 0

T M R 0

T M R 0 C

T M R 1 H

T M R 1 L

T M R 1 C

P A

P A C

P B

P B C

A D C R

R e s e r v e d

A D C D

I N T C 1

C H P R C

: U n u s e d

R e a d a s " 0 0 "

RAM Mapping

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