HT46R46E/HT46C46E

Rev. 1.30

19

July 19, 2005

Bit No.

Label

Function

0

1

ADCS0

ADCS1

Select the A/D converter clock source.

1, 1: Undefined

2~6

¾

Unused bit, read as

²0².

7

TEST

For internal test only.

ACSR (23H) Register

The following two programming examples illustrate how to setup and implement an A/D conversion. In the first exam-

ple, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,

whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.

Example: using EOCB Polling Method to detect end of conversion

clr

EADI

; disable ADC interrupt

mov

a,00000001B

mov

ACSR,a

mov

a,00100000B

; setup ADCR register to configure Port PB0~PB3 as A/D inputs

mov

ADCR,a

; and select AN0 to be connected to the A/D converter

:

:

; As the Port B channel bits have changed the following START

; signal (0-1-0) must be issued within 10 instruction cycles

:

Start_conversion:

clr

START

set

START

; reset A/D

clr

START

; start A/D

Polling_EOC:

sz

EOCB

; poll the ADCR register EOCB bit to detect end of A/D conversion

jmp

polling_EOC

; continue polling

mov

a,ADR

; read conversion result value from the ADR register

mov

adr_buffer,a

; save result to user defined memory

:

:

jmp

start_conversion

; start next A/D conversion

Example: using interrupt method to detect end of conversion

clr

EADI

; disable ADC interrupt

mov

a,00000001B

mov

ACSR,a

mov

a,00100000B

; setup ADCR register to configure Port PB0~PB3 as A/D inputs

mov

ADCR,a

; and select AN0 to be connected to the A/D converter

:

; As the Port B channel bits have changed the following START

; signal (0-1-0) must be issued within 10 instruction cycles

:

Start_conversion:

clr

START

set

START

; reset A/D

clr

START

; start A/D

clr

ADF

; clear ADC interrupt request flag

set

EADI

; enable ADC interrupt

set

EMI

; enable global interrupt

: