Pin Description

Pin Name

I/O

Option

Description

PA0~PA2

PA3/PFD

PA4/TMR

PA5/INT

PA6~PA7

I/O

Pull-high

Wake-up

PFD

I/O lines with pull-high resistors (bit option). I/O modes of each line are controlled

by related control register bit (PAC).

Each line of PA can be optioned as a wake-up input (bit option).

I/O configurations: Schmitt trigger/CMOS.

The PA3, PA4 and PA5 are pin-shared with PFD, TMR and INT, respectively.

PB0/AN0~

PB3/AN3

I/O

Pull-high

I/O lines with pull-high resistors (bit option).

I/O modes of each line are controlled by related control register bit (PBC).

I/O configurations: Schmitt trigger/CMOS.

Each PB line is pin shared with an A/D converter input.

PD0

I/O

Pull-high

I/O lines with pull-high resistors (bit option).

I/O modes of each line are controlled by related control register bit (PDC).

I/O configurations: Schmitt trigger/CMOS.

OSC1

OSC2

I

O

Crystal

or RC

A resistor connected across OSC1 and VSS or a crystal across OSC1 and OSC2

will generate the system clock.

RES

¾¾

Schmitt trigger reset input. Active low.

VDD

¾¾

Positive power supply

VSS

¾¾

Negative power supply, ground.

Note: All pull-high resistors are controlled by an option bit.

Absolute Maximum Ratings

Storage Temperature ............................

-50°Cto125°C

Operating Temperature...........................

-40°Cto85°C

Note: These are stress ratings only. Stresses exceeding the range specified under

²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those

listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-

ity.

HT45R06

Rev. 1.00

3

May 24, 2005