HT36M4

Rev. 1.00

6

August 15, 2005

Program Memory

- ROM

The program memory is used to store the program in-

structions which are to be executed. It also contains

data, table, and interrupt entries, and is organized into

8192

´16 bits, addressed by the bank pointer, program

counter and table pointer.

Certain locations in the program memory of each bank

are reserved for special usage:

This area is reserved for the initialization program. Af-

ter chip reset, the program always begins execution at

location 000H on bank0.

This area is reserved for the external interrupt service

program. If the INT input pin is activated, the interrupt

is enabled and the stack is not full, the program will

jump to location 004H and begins execution.

This area is reserved for the Timer/Event Counter 0 in-

terrupt service program on each bank. If timer interrupt

results from a Timer/Event Counter 0 overflow, and if the

interrupt is enabled and the stack is not full, the program

begins execution at location 008H corresponding to its

bank.

This area is reserved for the Timer/Event Counter 1

interrupt service program on each bank. If a timer in-

terrupt results from a Timer/Event Counter 1 overflow,

and if the interrupt is enabled and the stack is not full,

the program begins execution at location 00CH corre-

sponding to its bank.

Any location in the ROM space can be used as

look-up tables. The instructions

²TABRDC [m]² (the

current page, 1 page=256 words) and

²TABRDL [m]²

(the last page) transfer the contents of the lower-order

byte to the specified data memory, and the

higher-order byte to TBLH (08H). Only the destination

of the lower-order byte in the table is well-defined, the

higher-order byte of the table word are transferred to

the TBLH. The Table Higher-order byte register

(TBLH) is read only. The Table Pointer (TBLP) is a

read/write register (07H), which indicates the table lo-

cation. Before accessing the table, the location must

be placed in the TBLP. The TBLH is read only and

cannot be restored. If the main routine and the ISR

(Interrupt Service Routine) both employ the table read

instruction, the contents of the TBLH in the main rou-

tine are likely to be changed by the table read instruc-

tion used in the ISR. Errors can occur. In this case,

using the table read instruction in the main routine and

the ISR simultaneously should be avoided. However,

if the table read instruction has to be applied in both

the main routine and the ISR, the interrupt should be

disabled prior to the table read instruction. It will not be

enabled until the TBLH has been backed up. All table

related instructions need 2 cycles to complete the op-

eration. These areas may function as normal program

memory depending upon user requirements.

The program memory is organized into 8 banks and

each bank into 8192

´16 of bits program ROM. PF2~

PF0 is used as the bank pointer only when PFC is

configured as output mode. PFC is the control register

for PF and is used to control the input/output configu-

ration. To function as an output, the corresponding bit

of the control register must be

²0². After an instruction

has been executed to write data to the PF register to

select a different bank, note that the new bank will not

be selected immediately. It is not until the following in-

struction has completed execution that the bank will

be actually selected. It should be note that the PF reg-

ister has to be cleared before setting to output mode.

0 0 0 4 H

0 0 0 8 H

1 6 b i t s

P r o g r a m

R O M

n 0 0 H

1 F F F H

N o t e : n r a n g e s f r o m 0 0 t o 1 F .

n F F H

0 0 0 C H

T i m e r / e v e n t C o u n t e r 0 i n t e r r u p t s u b r o u t i n e

L o o k - u p t a b l e ( 2 5 6 w o r d s )

L o o k - u p t a b l e ( 2 5 6 w o r d s )

T i m e r / e v e n t C o u n t e r 1 i n t e r r u p t s u b r o u t i n e

E x t e r n a l i n t e r r u p t s u b r o u t i n e

D e v i c e i n i t i a l i z a t i o n p r o g r a m

0 0 0 0 H

Program Memory for Each Bank

Instruction (s)

Table Location

*12

*11

*10

*9

*8

*7

*6

*5

*4

*3

*2

*1

*0

TABRDC [m]

P12

P11

P10

P9

P8

@7

@6

@5

@4

@3

@2

@1

@0

TABRDL [m]

11111

@7

@6

@5

@4

@3

@2

@1

@0

Table Location

Note:

*12~*0: Bits of table location

@7~@0: Bits of table pointer

P12~P8: Bits of current Program Counter