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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC16F87-I/ML датащи(PDF) 44 Page - Microchip Technology |
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PIC16F87-I/ML датащи(HTML) 44 Page - Microchip Technology |
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44 / 214 page  PIC16F87/88 DS30487B-page 42 Preliminary 2003 Microchip Technology Inc. • Clock before switch: One of INTOSC/INTOSC postscaler (IRCF<2:0> ≠ 000) 1. IRCF bits are modified to a different INTOSC/ INTOSC postscaler frequency. 2. The clock switching circuitry waits for a falling edge of the current clock, at which point CLKO is held low. 3. The clock switching circuitry then waits for eight falling edges of requested clock, after which it switches CLKO to this new clock source. 4. The IOFS bit is set. 5. Oscillator switchover is complete. 4.6.6 OSCILLATOR DELAY UPON POWER-UP, WAKE-UP AND CLOCK SWITCHING Table 4-3 shows the different delays invoked for vari- ous clock switching sequences. It also shows the delays invoked for POR and wake-up. TABLE 4-3: OSCILLATOR DELAY EXAMPLES Switch From Switch To Frequency Oscillator Delay Comments SLEEP/POR INTRC T1OSC INTOSC/ INTOSC Postscaler 31.25 kHz 32.768 kHz 125kHz - 8MHz 5 µs - 10 µs (approx.) CPU Start-up(1) Following a wake-up from SLEEP mode or POR, CPU start-up is invoked to allow the CPU to become ready for code execution. INTRC/SLEEP EC, RC DC - 20 MHz INTRC (31.25 kHz) EC, RC DC - 20 MHz SLEEP LP, XT, HS 32.768 kHz - 20 MHz 1024 Clock Cycles (OST) Following a change from INTRC, an OST of 1024 cycles must occur. INTRC (31.25 kHz) INTOSC/ INTOSC Postscaler 125kHz - 8MHz 4ms Refer to Section 4.6.4 “Modifying the IRCF bits” for further details. Note 1: The 5 µs-10 µs start-up delay is based on a 1 MHz system clock. |
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