CC2430-RTR1-F64Z datasheet(206/234 Pages) TI

206 / 234 page

CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 206 of 232

Bit

Name

Reset

R/W

Description

SLOTTED_ACK

R/W

SLOTTED_ACK defines the timing of automatically

transmitted acknowledgment frames.

0 : The acknowledgment frame is transmitted 12 symbol

periods after the incoming frame.

1 : The acknowledgment frame is transmitted between 12

and 30 symbol periods after the incoming frame. The timing

is defined such that there is an integer number of 20-symbol

periods between the received and the transmitted SFDs.

This may be used to transmit slotted acknowledgment

frames in a beacon enabled network.

R/W

Reserved

CORR_THR_SFD

R/W

CORR_THR_SFD defines the level at which the

CORR_THR correlation threshold is used to filter out

received frames.

0 : Same filtering as CC2420, should be combined with a

CORR_THR of 0x14

1 : More extensive filtering is performed, which will result in

less false frame detections e.g. caused by noise.

4:0

CORR_THR[4:0]

0x10

R/W

Demodulator correlator threshold value, required before

SFD search.

Table 48: Register MDMCTRL1H (0xDF04)

Bit

Name

Reset

R/W

Description

7:6

Reserved, read as 0.

DEMOD_AVG_MODE

R/W

DC average filter behavior.

0 : Lock DC level to be removed after preamble match

1 : Continuously update DC average level.

MODULATION_MODE

R/W

Set one of two RF modulation modes for RX / TX

0 : IEEE 802.15.4 compliant mode

1 : Reversed phase, non-IEEE compliant (could be used to

set up a system which will not receive 802.15.4 packets)

3:2

TX_MODE[1:0]

R/W

Set test modes for TX

00 : Normal operation, transmit TXFIFO

01 : Serial mode, use transmit data on serial interface,

infinite transmission.

10 : TXFIFO looping ignore underflow in TXFIFO and read

cyclic, infinite transmission.

11 : Send random data from CRC, infinite transmission.

1:0

RX_MODE[1:0]

R/W

Set test mode of RX

00 : Normal operation, use RXFIFO

01 : Receive serial mode, output received data on pins.

Infinite RX.

10 : RXFIFO looping ignore overflow in RXFIFO and write

cyclic, infinite reception.

11 : Reserved

Table 49: Register MDMCTRL1L (0xDF05)

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