CC2430-RTR1-F64Z datasheet(178/234 Pages) TI

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CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 178 of 232

14.19 Acknowledge Frames

CC2430 includes hardware support for

transmitting

acknowledge

frames,

specified in [1]. Figure 50 shows the

format of the acknowledge frame.

If MDMCTRL0L.AUTOACK is enabled, an

acknowledge frame is transmitted for all

incoming frames accepted by the address

recognition with the acknowledge request

flag set and a valid CRC. AUTOACK

therefore does not make sense unless

also ADDR_DECODE and AUTOCRC are

enabled. The sequence number is copied

from the incoming frame.

Frame

Control Field

(FCF)

Data

Sequence

Number

Frame Check

Sequence

(FCS)

MAC Header (MHR)

MAC Footer

(MFR)

Frame

Length

Start of Frame

Delimiter

(SFD)

Bytes:

Preamble

Sequence

Synchronisation Header

(SHR)

PHY Header

(PHR)

Figure 50: Acknowledge frame format [1]

Two

command

strobes,

SACK

and

SACKPEND

are

defined

transmit

acknowledge frames with the frame

pending field cleared or set, respectively.

The

acknowledge

frame

only

transmitted if the CRC is valid.

For systems using beacons, there is an

additional timing requirement that the

acknowledge frame transmission may be

started on the first backoff-slot boundary

(20 symbol periods) at least 12 symbol

periods after the last symbol of the

incoming frame. When the RF register

control bit MDMCTRL1H.SLOTTED_ACK is

set to 1, the acknowledge frame is

transmitted between 12 and 30 symbol

periods after the incoming frame. The

timing is defined such that there is an

integer number of 20-symbol period

backoff-slots between the incoming packet

SFD and the transmitted acknowledge

frame SFD. This timing is also illustrated in

Figure 51.

Using SACKPEND will set the pending data

flag

for

automatically

transmitted

acknowledge frames using AUTOACK. The

pending flag will then be set also for future

acknowledge

frames,

until

SACK

command strobe is issued. The pending

data flag that is transmitted will be logically

OR’ed

with

the

value

FSMTC1.PENDING_OR. Thus the pending

flag can be set high using this register

control bit.

Acknowledge frames may be manually

transmitted

using

normal

data

transmission if desired.

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