CC2430-RTR1-F64Z datasheet(129/234 Pages) TI

129 / 234 page

CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 129 of 232

13.7.2.5 ADC Conversion Results

The

digital

conversion

result

represented in two's complement form. For

13-bit resolution the digital conversion

result is 8191 when the analog input is

equal to the VREF, and the conversion

result is -8192 when the analog input is

equal to –VREF, where VREF is the

selected positive voltage reference.

The digital conversion result is available

when ADCCON1.EOC is set to 1, in ADCH

and ADCL.

When the ADCCON2.SCH bits are read,

they will indicate which channel the

conversion result in ADCL and ADCH apply

to.

13.7.2.6 ADC Reference Voltage

The positive reference voltage for analog-

to-digital conversions is selectable as

either an internally generated 1.25V

voltage, the AVDD_SOC pin, the external

voltage applied to the AIN7 input pin or the

differential voltage applied to the AIN6-

AIN7 inputs.

It is possible to select the reference

voltage as the input to the ADC in order to

perform a conversion of the reference

voltage e.g. for calibration purposes.

Similarly, it is possible to select the ground

terminal GND as an input.

13.7.2.7 ADC Conversion Timing

The ADC runs on the 32 MHz system

clock, which is divided by 8 to give a 4

MHz

clock.

Both

the

delta

sigma

modulator and decimation filter use the 4

MHz clock for their calculations.

The time required to perform a conversion

depends on the selected decimation rate.

When the decimation rate is set to for

instance 128, the decimation filter uses

exactly 128 of the 4 MHz clock periods to

calculate the result. When a conversion is

started, the input multiplexer is allowed 16

4 MHz clock cycles to settle in case the

channel has been changed since the

previous conversion. The 16 clock cycles

settling time applies to all decimation

rates. Thus in general, the conversion time

is given by:

Tconv = (decimation rate + 16) x 0.25 µs.

13.7.2.8 ADC Interrupts

The ADC will generate an interrupt when

an extra conversion has completed. An

interrupt

not

generated

when

conversion

from

the

sequence

completed.

13.7.2.9 ADC DMA Triggers

The ADC will generate a DMA trigger

every

time

conversion

from

the

sequence has completed. When an extra

conversion completes, no DMA trigger is

generated.

There is one DMA trigger for each of the

eight channels defined by the first eight

possible settings for ADCCON2.SCH . The

DMA trigger is active when a new sample

is ready from the conversion for the

channel. The DMA triggers are named

ADC_CHx in Table 37 on page 92.

In addition there is one DMA trigger,

ADC_CHALL, which is active when new

data is ready from any of the channels in

the ADC conversion sequence.

13.7.2.10 ADC Registers

This section describes the ADC registers.

ADCL (0xBA) – ADC Data Low

Bit

Name

Reset

R/W

Description

7:2

ADC[5:0]

0x00

Least significant part of ADC conversion result.

1:0

Not used. Always read as 0

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