RT8249 datasheet(17/23 Pages) RICHTEK

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RT8249A/B/C

DS8249A/B/C-02

June 2014

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

IPEAK

ILOAD

ILIMIT

Figure 2.

“Valley” Current Limit

The RT8249A/B/C uses the on resistance of the

synchronous rectifier as the current sense element and

supports temperature compensated MOSFET RDS(ON)

sensing. The RILIM resistor between the CSx pin and GND

sets the current limit threshold. The resistor RILIM is

connected to a current source from CSx which is 50

μA

(typ.) at room temperature. The current source has a

4700ppm/

°C temperature slope to compensate the

temperature dependency of the RDS(ON). When the voltage

drop across the sense resistor or low-side MOSFET

equals 1/8 the voltage across the RILIM resistor, positive

current limit will be activated. The high-side MOSFET will

not be turned on until the voltage drop across the MOSFET

falls below 1/8 the voltage across the RILIM resistor.

Choose a current limit resistor according to the following

equation :

VLIMIT = (RLIMIT x 50

μA) / 8 = ILIMIT x RDS(ON)

RLIMIT = (ILIMIT x RDS(ON)) x 8 / 50

μA

Current Limit Setting

The RT8249A/B/C has cycle-by-cycle current limit control

and the OCP function only operation at CCM, it is disabled

at DEM in order to reduce quiescent current. The current

limit circuit employs a unique

“valley” current sensing

algorithm. If the magnitude of the current sense signal at

PHASEx is above the current limit threshold, the PWM

is not allowed to initiate a new cycle (Figure 2). The actual

peak current is greater than the current limit threshold by

an amount equal to the inductor ripple current. Therefore,

the exact current limit characteristic and maximum load

capability are a function of the sense resistance, inductor

value, battery and output voltage.

Figure 3. Charge Pump Circuit Connected to VCLK

MOSFET Gate Driver (UGATEx, LGATEx)

The high-side driver is designed to drive high current, low

RDS(ON) N-MOSFET(s). When configured as a floating driver,

5V bias voltage is delivered from the LDO5 supply. The

average drive current is also calculated by the gate charge

at VGS = 5V times switching frequency. The instantaneous

drive current is supplied by the flying capacitor between

the BOOTx and PHASEx pins. A dead-time to prevent

VCLK

VOUT1

Charge Pump

Carefully observe the PC board layout guidelines to ensure

that noise and DC errors do not corrupt the current sense

signal at PHASEx and GND. Mount or place the IC close

to the low-side MOSFET.

VCLK for Charge Pump

A 260kHz VCLK signal can be used for the external charge

pump circuit. The VCLK signal becomes available when

EN1 enters ON state. VCLK driver circuit is driven by BYP1

voltage. In a design that does not require VCLK output,

tie 200

Ω between VCLK pin and GND so that VCLK is

turned off. The accuracy of VCLK disable resistor is

recommended less than 5%.

The external 14V charge pump is driven by VCLK. As

shown in Figure 3, when VCLK is low, C1 will be charged

by VOUT1 through D1. C1 voltage is equal to VOUT1 minus

the diode drop. When VCLK becomes high, C1 transfers

the charge to C2 through D2 and charges C2 voltage to

VVCLK plus C1 voltage. As VCLK transitions low on the

next cycle, C3 is charged to C2 voltage minus a diode

drop through D3. Finally, C3 charges C4 through D4 when

VCLK switches high. Thus, the total charge pump voltage,

VCP, is :

VCP = VOUT1

+ 2 x VVCLK − 4 x VD

where VVCLK is the peak voltage of the VCLK driver which

is equal to LDO5 and VD is the forward voltage dropped

across the Schottky diode.

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