Output Current (A)

0

0.2

0.4

0.6

0.8

1

1.2

-6

-4

-2

0

2

4

6

+85

C

+25

C

−40

C

Figure 8-4. Output Headroom vs Output Current

Output Current (mA)

-800

-600

-400

-200

0

200

400

600

800

-8

-6

-4

-2

0

2

4

6

8

2W Internal Power Dissipation SOA Curve

100

 Load Line

10

 Load Line

Figure 8-5. Output Voltage and Current Limitations

For the specifications described previously, consider voltage and current limits separately. In many applications,

it is the voltage times the current (or V-I product) that is more relevant to circuit operation. See Figure 8-5.

Figure 8-5 shows the zero-voltage output current limit and the zero-current output voltage limit on the X- and

Y-axes, respectively. The four quadrants give a more detailed view of the OPA2675 output drive capabilities,

noting that the graph is bounded by a safe operating area of 2W maximum internal power dissipation (in this

case, for one channel only). Superimposing resistor load lines onto the plot shows that the OPA2675 can drive

±4 V into 10 Ω or ±4.5 V into 25 Ω without exceeding the output capabilities or the 2-W dissipation limit.

8.3.1.3 Driving Capacitive Loads

One of the most demanding and yet very common load conditions for an op amp is capacitive loading.

The capacitive load is often the input of an analog-to-digital converter (ADC), including additional external

capacitance that may be recommended to improve the ADC linearity. A high-speed, high open-loop gain

amplifier such as the OPA2675 can be very susceptible to decreased stability and closed-loop response peaking

when a capacitive load is placed directly on the output pin. When the amplifier open-loop output resistance is

considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase

margin.

402

133

R

ISO

+V

S

–V

S

OPA2675

49.9

C

L

V

I

R

LOAD

Figure 8-6. Driving a Large Capacitive Load Using an Output Series Isolation Resistor

When the primary considerations are frequency response flatness, pulse response fidelity, and distortion, the

approach does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher

frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the

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OPA2675

SBOSAA5B – APRIL 2022 – REVISED SEPTEMBER 2022

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