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OPA656 датащи(PDF) 16 Page - Texas Instruments |
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OPA656 датащи(HTML) 16 Page - Texas Instruments |
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16 / 25 page ![]() 2. Minimize the distance (less than 0.25-in) from the power-supply pins to high-frequency decoupling capacitors. Use high quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage ratings at least three times greater than the amplifiers maximum power supplies to ensure that there is a low-impedance path to the amplifiers power-supply pins across the amplifiers gain bandwidth specification. At the device pins, do not allow the ground and power plane layout to be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections must always be decoupled with these capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors, effective at lower frequency, must be used on the supply pins. These are placed further from the device and are shared among several devices in the same area of the PC board. 3. Careful selection and placement of external components will preserve the high frequency performance of the OPA817. Use low-reactance resistors. Surface-mount resistors work best and allow a tighter overall layout. Never use wirewound type resistors in a high frequency application. Because the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the inverting input and the output pin, respectively. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Even with a low parasitic capacitance at the noninverting input, high external resistor values can create significant time constants that can degrade performance. When OPA817 is configured as a conventional voltage amplifier, keep the resistor values as low as possible and consistent with the load driving considerations. Decreasing the resistor values keeps the resistor noise terms low and minimizes the effect of the parasitic capacitance. However, lower resistor values increase the dynamic power consumption because RF and RG become part of the output load network of the amplifier 4. Heat dissipation is important for a high voltage device like OPA817. For good thermal relief, the thermal pad should be connected to a heat spreading plane that is preferably on the same layer as OPA817 or connected by as many vias as possible, if the plane is on a different layer. It is recommended to have at least one heat spreading plane on the same layer as the OPA817 that makes a direct connection to the thermal pad with wide metal for good thermal conduction when operating at high ambient temperatures. If more than one heat spreading plane is available, then connect them by a number of vias to further improve the thermal conduction. 11.1.1 Thermal Considerations The OPA817 will not require heatsinking or airflow in most applications. Maximum allowed junction temperature will set the maximum allowed internal power dissipation as described in the following paragraph. In no case should the maximum junction temperature be allowed to exceed 150°C. Operating junction temperature (TJ) is given by TA + PD × RθJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load, but for a grounded resistive load the PDL will be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for balanced bipolar supplies). Under this condition PDL = VS 2/(4 × RL) where RL includes feedback network loading. Note that it is the power in the output stage and not into the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using OPA817 in the circuit of Figure 9-1 operating at the maximum specified ambient temperature of +105°C and driving a grounded 100-Ω load. PD = 10 V × 23.5 mA + 52 /(4 × (100 Ω || 500 Ω)) ≅ 310 mW Maximum TJ = 105°C + (0.310 W × 64.9°C/W) = 125.1°C. All actual applications will be operating at lower internal power and junction temperature. OPA817 SBOS847 – JULY 2022 www.ti.com 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: OPA817 |
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