7.3.4 Open-Drain Digital Output

The AMC22C11-Q1 provides an open-drain output with optional latching function. The output is actively pulled

The open-drain output is diode-connected to the VDD2 supply (see the Functional Block Diagram), meaning that

the output cannot be pulled more than 500 mV above the VDD2 supply before significant current begins to flow

into the OUT pin. In particular, the open-drain output is clamped to one diode voltage above ground if VDD2 is at

the GND2 level. This behavior is indicated by the gray shadings in Figure 7-5 through Figure 7-10.

On a system level, the CMTI performance of an open-drain signal line depends on the value of the pullup

resistor. During a common-mode transient event with a high slew rate (high dV/dt), the open-drain signal line

may be pulled low due to parasitic capacitive coupling between the high-side and the low-side of the printed

circuit board (PCB). The effect of the parasitic coupling on the signal level is a function of the pullup strength and

a lower value pullup resistor results in better CMTI performance. The AMC22C11-Q1 has been characterized

with a relatively weak pullup resistor value of 10 kΩ to ensure that the specified CMTI performance is met in a

typical application with a 4.7 kΩ or lower pullup resistor.

7.3.4.1 Transparent Output Mode

The device is set to transparent mode when the LATCH pin is pulled low, thus allowing the output state to

change and follow the input signal with respect to the programmed trip threshold. For example, when the

input signal rises above the trip threshold, the OUT pin is pulled low. When the input signal drops below the

trip threshold, the output returns to the default high output state. A common implementation using the device

in transparent mode is to connect the OUT pin to a hardware interrupt input on a controller. As soon as an

out-of-range condition is detected by the device and the OUT pin is pulled low, the controller interrupt terminal

detects the output state change and can begin making changes to the system operation needed to address the

out-of-range condition.

7.3.4.2 Latch Output Mode

Some applications do not have the functionality available to continuously monitor the state of the OUT pin to

detect an overcurrent condition. A typical example of this application is a system that is only able to poll the OUT

terminal state periodically to determine if the system is functioning correctly. If the device is set to transparent

mode in this type of application, a change in the state of the OUT pin can be missed if the out-of-range condition

does not appear during one of these periodic polling events.

Latch mode is specifically intended to accommodate these applications. The device is placed in latch mode

by setting the voltage on the LATCH terminal to a logic high level. The difference between latch mode and

transparent mode is how the output responds when an out-of-range event ends. In transparent mode, when the

input signal drops below the trip threshold, the output state returns to the default high setting to indicate that the

out-of-range event has ended.

In latch mode, when an out-of-range condition is detected and the OUT pin is pulled low, the OUT pin does not

return to the default high level when the input signal drops below the trip threshold level. To clear the event, the

LATCH terminal must be pulled low for at least 4 μs. Pulling the LATCH pin low allows the OUT pin to return to

the default high level, provided that the input signal has dropped below the trip threshold. If the input signal is still

above the threshold when the LATCH pin is pulled low, the OUT terminal remains low. When the out-of-range

event is detected by the system controller, the LATCH pin can be set back to high in order to place the device

back into latch mode.

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AMC23C11-Q1

SBASAJ7A – JUNE 2022 – REVISED AUGUST 2022

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