HS401x Datasheet

R36DS0023EU0103 Rev.1.03

Jun 6, 2022

Page 9

4.1

rates. Each transmission is initiated when the master sends a 0 START bit (S), and the transmission is

terminated when the master sends a 1 STOP bit (P). These bits are exclusively transmitted while the SCL line is

high.

SDA

SCL

Figure 12. Timing Diagram

Parameter

Symbol

Minimum

Typical

Maximum

Unit

SCL Clock Frequency

0

-

400

kHz

START Condition Hold Time Relative to SCL Edge

0.1

-

-

µs

Minimum SCL Clock LOW Width [1]

0.6

-

-

µs

Minimum SCL Clock HIGH Width [1

0.6

-

-

µs

START Condition Setup Time Relative to SCL Edge

0.1

-

-

µs

Data Hold Time on SDA Relative to SCL Edge

0

-

0.5

µs

Data Setup Time on SDA Relative to SCL Edge

0.1

-

-

µs

STOP Condition Setup Time on SCL

0.1

-

-

µs

Bus Free Time Between STOP Condition and START

Condition

1

-

-

µs

1.

Combined LOW and HIGH widths must equal or exceed the minimum SCL period.

4.2

Sensor Slave Address

4.4 for further information.

4.3

The sensor transmission is initiated when the master sends a 0 START bit (S). The transmission is terminated

when the master sends a 1 STOP bit (P). These bits are only transmitted while the SCL line is HIGH (see Figure

13 for waveforms).

Once the START condition has been set, the SCL line is toggled at the prescribed data rate, clocking

subsequent data transfers. Data on the SDA line is always sampled on the rising edge of the SCL line and must

remain stable while SCL is HIGH to prevent false START or STOP conditions.