DPD Demodulator for PA Linearization

1300MHz to 2900MHz

IDT Zero-Distortion

7

Rev4, January 2014

PRELIMINARY DATASHEET

IDTF1370NBGI

Datasheet

If CSb is de-asserted (set to high), the serial interface will ignore the CLK line. Once CSb is asserted (set to low), the

serial interface will recognize the CLK and any data present on DATA will be clocked into the registers with each

rising CLK edge. After the 16

program the part with the desired bytes. If CSb is de-asserted before the 16

there is no guarantee that the correct bytes will be programmed and the user will have to re-program the interface in

accordance with the aforementioned procedure.



When SW_LATCH is pinned high during the programming sequence, “RFSW” and “ENb” registers cannot be

programmed and therefore will not toggle.



If SW_LATCH is pinned low during the programming sequence, the “RFSW” and “ENb” register will

toggle.

This can be prevented with the “Programming Sequence” below.

1) SW_Latch = 1; CSb = 0

2) CLK in 8- or 16-bit word, do not de-assert (pull high) CSb

3) Set SW_LATCH = 0 while CSb = 0 remains)

4) With SW_Latch = 0, set CSb = 1

5) Set SW_Latch = 1

6) Program complete

SDATA

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SCLK

0

0

0

0

0

1

0

1

RFSW

ENb

CSb (solid)

SW_LATCH (dashed)

RFSW