поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

WM8501 датащи(PDF) 8 Page - Wolfson Microelectronics plc

номер детали WM8501
подробное описание детали  24-bit 192kHz Stereo DAC with 1.7Vrms Line Driver
PDF  20 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  WOLFSON [Wolfson Microelectronics plc]
домашняя страница  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8501 датащи(HTML) 8 Page - Wolfson Microelectronics plc

Back Button WM8501 Datasheet HTML 4Page - Wolfson Microelectronics plc WM8501 Datasheet HTML 5Page - Wolfson Microelectronics plc WM8501 Datasheet HTML 6Page - Wolfson Microelectronics plc WM8501 Datasheet HTML 7Page - Wolfson Microelectronics plc WM8501 Datasheet HTML 8Page - Wolfson Microelectronics plc WM8501 Datasheet HTML 9Page - Wolfson Microelectronics plc WM8501 Datasheet HTML 10Page - Wolfson Microelectronics plc WM8501 Datasheet HTML 11Page - Wolfson Microelectronics plc WM8501 Datasheet HTML 12Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 20 page
background image
WM8501
Pre-Production
w
PP Rev 3.1 May 2006
8
MASTER CLOCK TIMING
MCLK
t
MCLKL
t
MCLKH
t
MCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
VDD = 5V, GND = 0V, TA = +25
oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK Master clock pulse width high
tMCLKH
8
ns
MCLK Master clock pulse width low
tMCLKL
8
ns
MCLK Master clock cycle time
tMCLKY
20
ns
MCLK Duty cycle
40:60
60:40
Time from MCLK stopping to power
down.
1.5
12
µs
DIGITAL AUDIO INTERFACE
Figure 2 Digital Audio Data Timing
Test Conditions
VDD = 5V, GND = 0V, TA = +25
oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
40
ns
BCLK pulse width high
tBCH
16
ns
BCLK pulse width low
tBCL
16
ns
LRCLK set-up time to BCLK
rising edge
tLRSU
8
ns
LRCLK hold time from
BCLK rising edge
tLRH
8
ns
DIN set-up time to BCLK
rising edge
tDS
8
ns
DIN hold time from BCLK
rising edge
tDH
8
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com