XRT72L50 datasheet(9/471 Pages) EXAR

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XRT72L50

SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

REV. 1.2.1

VII

TABLE 40: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK

(METHOD 2) .................................................................................................................................................. 216

Figure 78. The Terminal Equipment being interfaced to the Receive Overhead Data Output Interface (Method 2) ... 217

TABLE 41: THE RELATIONSHIP BETWEEN THE NUMBER OF RXOHENABLE OUTPUT PULSES ((SINCE RXOHFRAME WAS LAST

SAMPLED

"HIGH") TO THE DS3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE RXOH OUTPUT PIN ................. 218

4.3.5 The Receive Payload Data Output Interface ......................................................................................... 220

Figure 79. Illustration of the signals that are output via the Receive Overhead Data Output Interface block (for Method 2).

220

Figure 80. The Receive Payload Data Output Interface block .................................................................................... 220

TABLE 42: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK

221

4.3.5.1 Serial Mode Operation ................................................................................................................ 222

Figure 81. The XRT72L50 DS3/E3 Framer IC being interfaced to the Receive Terminal Equipment (Serial Mode Operation)

222

4.3.5.2 Nibble-Parallel Mode Operation .................................................................................................. 223

Figure 82. An Illustration of the behavior of the signals between the Receive Payload Data Output Interface block of the

XRT72L50 and the Terminal Equipment (Serial Mode Operation) .............................................................. 223

Figure 83. The XRT72L50 DS3/E3 Framer IC being interfaced to the Receive Section of the Terminal Equipment (Nibble-

Parallel Mode Operation) ............................................................................................................................. 224

4.3.6 Receive Section Interrupt Processing ................................................................................................... 225

4.3.6.1 Enabling Receive Section Interrupts ........................................................................................... 225

Figure 84. An Illustration of the Behavior of the signals between the Receive Payload Data Output Interface Block of the

XRT72L50 and the Terminal Equipment (Nibble-Mode Operation). ............................................................ 225

4.3.6.2 Enabling/Disabling and Servicing Receive Section Interrupts .................................................... 226

5.0 E3/ITU-T G.751 Operation of the XRT72L50 .................................................................................... 239

5.1 DESCRIPTION OF THE E3, ITU-T G.751 FRAMES AND ASSOCIATED OVERHEAD BITS ........................................... 239

5.1.1 Definition of the Overhead Bits ............................................................................................................. 239

5.1.1.1 The A (Alarm) Bit ........................................................................................................................ 239

Figure 85. Illustration of the E3, ITU-T G.751 Framing Format. .................................................................................. 239

5.1.1.2 The N Bit ..................................................................................................................................... 240

5.2 THE TRANSMIT SECTION OF THE XRT72L50 (E3, ITU-T G.751 MODE OPERATION) ........................................... 240

5.2.1 The Transmit Payload Data Input Interface Block ................................................................................. 241

Figure 86. The XRT72L50 Transmit Section configured to operate in the E3 Mode ................................................... 241

Figure 87. The Transmit Payload Data Input Interface Block ...................................................................................... 241

TABLE 43: LISTING AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE TRANSMIT PAYLOAD DATA INPUT INTERFACE ... 242

5.2.1.1 Mode 1 - The Serial/Loop-Timing Mode The Behavior of the XRT72L50 ................................... 243

Figure 88. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 1 (Serial/

Loop-Timed) Operation ............................................................................................................................... 244

Figure 89. Behavior of the Terminal Interface signals between the XRT72L50 Transmit Payload Data Input Interface block

and the Terminal Equipment (for Mode 1 Operation) ................................................................................... 246

5.2.1.2 Mode 2 - The Serial/Local-Timed/Frame-Slave Mode Behavior of the XRT72L50 ..................... 247

Figure 90. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 2 (Serial/

Local-Timed/Frame-Slave) Operation .......................................................................................................... 247

Figure 91. Behavior of the Terminal Interface signals between the XRT72L50 and the Terminal Equipment (Mode 2

Operation) .................................................................................................................................................... 248

5.2.1.3 Mode 3 - The Serial/Local-Timed/Frame-Master Mode Behavior of the XRT72L50 ................... 249

Figure 92. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 3 (Serial/

Local-Timed/Frame-Master) Operation ........................................................................................................ 250

5.2.1.4 Mode 4 - The Nibble-Parallel/Loop-Timed Mode Behavior of the XRT72L50 ............................. 251

Figure 93. Behavior of the Terminal Interface signals between the XRT72L50 and the Terminal Equipment (E3 Mode 3

Operation) .................................................................................................................................................... 251

Figure 94. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 4 (Nibble-

Parallel/Loop-Timed) Operation ................................................................................................................... 252

Figure 95. Behavior of the Terminal Interface signals between the XRT72L50 and the Terminal Equipment (Mode 4

Operation) .................................................................................................................................................... 253

5.2.1.5 Mode 5 - The Nibble-Parallel/Local-Timed/Frame-Slave Interface Mode Behavior of the XRT72L50

254

Figure 96. The Terminal Equipment being interfaced to the Transmit Payload Data Input Interface block for Mode 5 (Nibble-

Parallel/Local-Timed/Frame-Slave) Operation ............................................................................................. 255

5.2.1.6 4.2.1.6 Mode 6 - The Nibble-Parallel/Local-Timed/Frame-Master Interface Mode Behavior of the

XRT72L50 ............................................................................................................................................... 256

Figure 97. Behavior of the Terminal Interface signals between the XRT72L50 and the Terminal Equipment (E3, Mode 5

Operation) .................................................................................................................................................... 256

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