25CSM04T-ISLASHCS0668 datasheet(22/55 Pages) MICROCHIP

22 / 55 page

25CSM04

DS20005817D-page 22

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6.1.3

WRITE ENABLE LATCH

Enabling and disabling writing to any nonvolatile

is accomplished through the Write Enable instruction

(WREN) as shown in Section 5.1 “Write Enable

Instruction (WREN)” and the Write Disable instruction

(WRDI) as shown in Section 5.2 “Write Disable

Instruction (WRDI)”. These functions change the

state of the Write Enable Latch (WEL) bit (byte 0, bit 1)

in the STATUS register.

6.1.4

READY/BUSY STATUS LATCH

The Ready/Busy Status Latch (RDY/BSY) is used to

indicate whether the device is currently active in a

nonvolatile write sequence. This bit is read-only and

automatically updated by the device. This bit is

provided in bit 0 of both STATUS register bytes.

A logic ‘1’ bit indicates that the device is currently busy

performing a nonvolatile write sequence. During this

time, only the Read STATUS Register (RDSR) and the

Write Ready/Busy Poll (WRBP) instructions will be

executed by the device.

A logic ‘0’ bit in this position indicates the device is

ready to accept new instructions.

6.1.4.1

Write Ready/Busy Poll

The Write Ready/Busy Poll (WRBP) instruction provides

direct access to the Ready/Busy STATUS register bit in

an 8-bit format. The WRBP instruction can be used after

any nonvolatile write sequence as a means to check if

the device has completed its internal write cycle.

This instruction will return an FFh value when the

device is still busy completing the write cycle or a 00h

value if the device is no longer in a write cycle.

Refer to Section 8.3 “Polling Routine” for a

description on implementing a polling routine.

Continuous reading of the WRBP state is supported

and the value output by the device will be updated

every eight bits.

FIGURE 6-1:

WRITE READY/BUSY POLL (WRBP) SEQUENCE

6.1.5

WRITE PROTECTION MODE BIT

The 25CSM04 write protection behavior is controlled

by the nonvolatile Write Protection Mode (WPM) bit in

the STATUS register. This bit is located in bit 7, byte 1

of the STATUS register. A logic ‘0’ indicates the device

is in Legacy Write Protection mode whereas a logic ‘1’

indicates the device is in Enhanced Write Protection

mode.

The write protection modes control how the contents of

the EEPROM and Security register as well as the

various nonvolatile registers in the device can be

inhibited from writing. An overview of the two protection

modes

can

found

Section 4.5

“Write

Protection”. Details on which nonvolatile registers are

protected, in conjunction with the WP pin, can be found

in Section 6.1.1 “Write-Protect Enable Bit”.

The WPM bit in the STATUS register can only be

modified using the WRSR instruction as described in

Section 6.3 “Write STATUS Register (WRSR)”.

Write protection mode can be made permanent by

executing the FRZR instruction. This can be done in

both Legacy Write Protection mode and Enhanced

Write Protection mode. Refer to Section 4.5.4 “Freeze

Memory Protection Configuration (FRZR)” for

additional information.

1213

1415

FFh or 00h Data Out

High-Impedance

SCK

WRBP Opcode (08h)

MSb

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