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LT8685SRVPBF датащи(PDF) 15 Page - Analog Devices

номер детали LT8685SRVPBF
подробное описание детали  42V Quad, Gangable, Synchronous, Monolithic Step-Down Regulator
PDF  24 Pages
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LT8685SRVPBF датащи(HTML) 15 Page - Analog Devices

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LT8685S
15
Rev. 0
For more information www.analog.com
APPLICATIONS INFORMATION
Similar to the EN/UVLO pin, the accurate 0.81V reference
of the EN2, EN3 and EN4 pins enables a programma-
ble undervoltage lockout feature for each correspond-
ing channel, realized by connecting an external resistor
divider between the respective channel’s input supply pin
and its EN pin.
The individual channel UVLO divider circuit is shown in
Figure 2. The threshold is given by:
V(CHAN_UVLO) =
RUV1+RUV2
RUV2
• 0.81V
RUV2
RUV1
ENx
VINx
LT8685S
8685S F02
Figure 2. Individual Channel UVLO Resistor Divider Connection
SWITCHING FREQUENCY
Each channel operates from a clock provided by an
internal oscillator whose frequency is determined by an
external resistor connected from the RT pin to ground.
By selecting the appropriate external resistor value, the
switching frequency may be programmed from 350kHz
to 3MHz.
Table 1 shows the recommended value of the RT resistor
for some common switching frequencies.
Table 1. Switching Frequency (fSW) vs RT Value
SWITCHING FREQUENCY (MHz)
RT (kΩ)
0.35
154
0.5
107
0.75
69
1
49.9
1.25
39
1.5
32
1.75
26.4
2
22.6
2.25
19.6
2.5
17.2
2.75
15.4
3
13.7
The following equation approximates the values shown
in Table 1.
RT =
55.4
fSW – 0.002
– 5
Where fSW is in MHz, and RT is in kΩ. The RT pin is sen-
sitive to noise so the resistor should be placed close to
the LT8685S and away from noise sources.
The oscillator generates four clock phases. When operat-
ing independently, the relative phases of the channels are
0° for CH1, 180° for CH2, 270° for CH3 and 90° for CH4.
When combining channels, the master channel phase
determines the combined channel’s clock phase.
COMBINING CHANNELS
The LT8685S provides the ability to combine multiple
regulators to create a single regulator capable of greater
output current using a single inductor.
The allowed channel combinations are given in Table 2.
Table 2. Allowed Channel Combinations
CONFIGURATION
NUMBER OF INDEPENDENT REGULATORS
1
1, 2, 3, 4
4
2
1, 2, 3 + 4
3
3
1 + 2, 3, 4
3
4
1 + 2, 3 + 4
2
When combining, the lowest numbered channel assumes
control of the combined regulators. For example, with
channel 1 and channel 2 combined, channel 1 assumes
control (master) and channel 2 becomes dependent
(slave). A feedback network is connected only to the
master channel to program the combined regulator out-
put voltage. The slave channel’s feedback pin must be
connected to INTVCC.
Combined channels must have a low impedance connec-
tion between their respective VIN pins, SW pins, and BST
pins. Only a single inductor is connected to the com-
bined SW pins. Though combined channels’ BST pins
are connected together, each channel should retain their
individual boost capacitors.



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