MPC9993

MOTOROLA

TIMING SOLUTIONS

2

Figure 2. 32–Lead Pinout (Top View)

GND

25

26

27

28

29

30

31

32

15

14

13

12

11

10

9

12345

678

24

23

22

21

20

19

18

17

16

MPC9993

Ext_FB

Ext_FB

GND

Clk_Selected

Inp1bad

Inp0bad

VCC

PLL_En

Man_Override

VCC_PLL

VCC

Qa0

Qa0

Qa1

Qa1

PIN DESCRIPTIONS

Pin Name

I/O

Pin Definition

CLK0, CLK0

CLK1, CLK1

LVPECL Input

LVPECL Input

Differential PLL clock reference (CLK0 pulldown, CLK0 pullup)

Differential PLL clock reference (CLK1 pulldown, CLK1 pullup)

Ext_FB, Ext_FB

LVPECL Input

Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup)

Qa0:1, Qa0:1

LVPECL Output

Differential 1x output pairs

Qb0:2, Qb0:2

LVPECL Output

Differential 2x output pairs

Inp0bad

LVCMOS Output

Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output

is active HIGH and will remain HIGH until the alarm reset is asserted

Inp1bad

LVCMOS Output

Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output

is active HIGH and will remain HIGH until the alarm reset is asserted

Clk_Selected

LVCMOS Output

‘0’ if clock 0 is selected, ‘1’ if clock 1 is selected

Alarm_Reset

LVCMOS Input

‘0’ will reset the input bad flags and align Clk_Selected with Sel_Clk. The input is “one–shotted”

(50k

Ω pullup)

Sel_Clk

LVCMOS Input

‘0’ selects CLK0, ‘1’ selects CLK1 (50k

Ω pulldown)

Manual_Override

LVCMOS Input

‘1’ disables internal clock switch circuitry (50k

Ω pulldown)

PLL_En

LVCMOS Input

‘0’ bypasses selected input reference around the phase–locked loop (50k

Ω pullup)

MR

LVCMOS Input

‘0’ resets the internal dividers forcing Q outputs LOW. Asynchronous to the clock (50k

Ω pullup)

VCCA

Power Supply

PLL power supply

VCC

Power Supply

Digital power supply

GNDA

Power Supply

PLL ground

GND

Power Supply

Digital ground