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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TDF8599BTH датащи(PDF) 24 Page - NXP Semiconductors |
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TDF8599BTH датащи(HTML) 24 Page - NXP Semiconductors |
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24 / 54 page  NXP Semiconductors TDF8599B I2C-bus controlled dual channel 43 W/2 Ohm, single channel 85 W/1 Ohm class-D power amplifier with load diagnostics TDF8599B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet Rev. 2 — 23 August 2016 24 / 54 Table 14. Instruction byte descriptions Bit Value Description Instruction byte IB1 Instruction byte IB2 Instruction byte IB3 D7 0 offset detection on pin DIAG offset protection on latch information on pins ADS and MOD when the amplifier starts switching 1 no offset detection on pin DIAG offset protection off latch information on pins ADS and MOD; see Section 9 D6 0 channel 1 offset monitoring on channel 2 offset monitoring on - 1 channel 1 offset monitoring off channel 2 offset monitoring off - D5 0 channel 1 clip detect on pin CLIP channel 2 clip detect on pin CLIP - 1 channel 1 no clip detect on pin CLIP channel 2 no clip detect on pin CLIP - D4 0 disable frequency hopping thermal pre-warning on pin CLIP disable AC load detection 1 enable frequency hopping[1] no thermal pre warning on pin CLIP enable AC load detection D3 0 oscillator frequency as set with Rosc − 10 % temperature pre-warning at 140 °C 1 oscillator frequency as set with Rosc + 10 % temperature pre-warning at 120 °C D2 0 - DC-load detection disabled 1 - DC-load detection enabled D1 0 channel 1 enabled channel 2 enabled 1 channel 1 disabled channel 2 disabled oscillator phase shift bits IB3[D3] to IB3[D1][2] D0 0 TDF8599B in Standby mode all channels operating AD modulation 1 TDF8599B in Mute or Operating modes[3] all channels muted BD modulation [1] See Section 8.3.3 for information on IB1[D4] and IB[D3]. [2] See Table 15 for information on IB3[D3] to IB3[D1]. [3] See Table 4for information on IB1[D0] and IB2[D0]. Table 15. Phase shift bit settings D3 D2 D1 Phase 0 0 0 0 0 0 1 1/4 π 0 1 0 1/3 π 0 1 1 1/2 π 1 0 0 2/3 π 1 0 1 3/4 π |
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