ＳＴＣ４８５Ｅ Ｄａｔａｓｈｅｅｔ Ｒｅｖ．０．１， Ｄｅｃ．２００５
Ｐａｇｅ ｏｆ １１
７
ＳＴＣ Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｌｉｍｉｔｅｄ ｈｔｔｐ：／／ｗｗｗ．ｍｃｕ－ｍｅｍｏｒｙ．ｃｏｍ
Detailed Description
The STC485E high-speed transceivers for RS-485 communication contain one driver and one receiver. These devices feature fail-safe
circuitry, which guarantees a logic-high receiver output when the receiver inputs are open or shorted, or when they are connected to
a terminated transmission line with all drivers disabled (see the Fail-Safe section). The STC485E feature reduced slew-rate drivers
that minimize EMI and reduce reflections caused by improperly terminated cables, allowing error-free data transmission up to
500kbps (see the Reduced EMI and Reflections section).
All of these parts operate from a single +5V supply. Drivers are output short-circuit current limited. Thermal shutdown circuitry
protects drivers against excessive power dissipation. When activated, the thermal shutdown circuitry places the driver outputs into
a high impedance state.
Fail-Safe
The STC485E guarantees a logic-high receiver output when the receiver inputs are shorted or open, or when they are connected to a
terminated transmission line with all drivers disabled. This is done by setting the receiver threshold between –50 mV and -200mV. If
the differential receiver input voltage (A-B) is greater than or equal to -50mV, RO is logic high. If A-B is less than or equal to -200mV,
RO is logic low. In the case of a terminated bus with all transmitters disabled, the receiver’
s differential input voltage is pulled to 0V
by the termination. With the receiver thresholds of the STC485E, , this results in a logic high with a 50mV minimum noise margin.
Unlike previous fail-safe devices, the -50mV to -200mV threshold complies with the ±200 mV EIA/TIA-485 standard.
±15kV ESD Protection
As with all STC devices, ESD-protection structures are incorporated on all pins to protect against electrostatic dis-
charges encountered during handling and assembly. The driver outputs and receiver inputs of the STC485E have extra
protection against static electricity. Union’s engineers have developed state-of-the-art structures to protect these pins
against ESD of ±15kV without damage.
The ESD-protected pins are tested with reference to the ground pin in a powered-down condition. They are tested to
±15kV using the Human Body Model.
ESD Test Conditions
ESD performance depends on a variety of conditions. Contact Union for a reliability report that documents test setup, test
methodology, and test results.
Human Body Model
Machine Model
The Machine Model for ESD tests all pins using a 200pF storage capacitor and zero discharge resistance. The objective is to emulate
the stress caused when I/O pins are contacted by handling equipment during test and assembly. All pins require this protecduring test
and assembly. All pins require this protection, not just RS-485 inputs and outputs.
Figure 11a shows the Human Body Model and Figure 11b shows the current waveform it generates when discharged into a low
impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest which is then discharged into the
test device through a 1.5k? ?resistor.
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