TUSB1004 datasheet(3/53 Pages) TI

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4 Pin Configuration and Functions

Thermal

pad

SSRX2p

SSRX2n

SSTX2p

SSTX2n

VIO_SEL

SSTX1p

SSTX1n

MODE

SSRX1p

SSRX1n

VCC

CEQ1

CRX1n

CRX1p

CTX1n

CTX1p

SSEQ0/A0

CTX2n

CTX2p

CEQ0

CRX2n

CRX2p

Not to scale

Figure 4-1. TUSB1004 RNQ Package, 40-Pin WQFN (Top View)

Table 4-1. Pin Functions

TYPE(1)

DESCRIPTION

NAME

NO.

VCC

3.3 V supply

SSEQ1/A1

4-level I

(PU/PD)

In I2C mode, this pin along with A0 pin selects the 7-bit I2C target address (refer to Table

7-7). In pin-strap mode, this pin along with SSEQ0 selects the receiver EQ for SSTX1

and/or SSTX2 (refer to Table 7-3).

EQCFG

4-level I

(PU/PD)

In pin-strap mode, this controls how CEQ[1:0] pins and SSEQ[1:0] are used. Refer to

Section 7.4.2 for details. In I2C mode, this pin is for TI internal test and must be left floating

for normal operation.

SLP_S0#

(PU)

SLP_S0#. This pin will control whether or not Rx.Detect function is enabled. If this pin is

low and device is in Disconnect state, Rx termination will be disabled. If this pin is low and

device is U2/U3 state, Rx termination will be enabled.

1: Rx.Detect Enabled.

0: Rx.Detect Disabled.

No internal connection.

VCC

3.3 V supply

TESTOUT1

For internal TI test only. For normal operation this pin should be left unconnected.

TESTOUT2

For internal TI test only. For normal operation this pin should be left unconnected.

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TUSB1004

SLLSFL3 – APRIL 2022

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