ATAR080-D datasheet(44/68 Pages) ATMEL

44 / 68 page

ATAR080

4675D–4BMCU–12/04

Figure 45. Example of 8-bit Synchronous Transmit Operation

Figure 46. Example of 8-bit Synchronous Receive Operation

9-bit Shift Mode

In the 9-bit shift mode, the SSI is able to handle the MCL protocol (described below). It

always operates as an MCL master device, i.e., SC is always generated and output by

the SSI. Both the MCL start and stop conditions are automatically generated whenever

the SSI is activated or deactivated by the SIR-bit. In accordance with the MCL protocol,

the output data is always changed in the clock low phase and shifted in on the high

phase.

Before activating the SSI (SIR = 0) and commencing an MCL dialog, the appropriate

data direction for the first word must be set using the SDD control bit. The state of this

bit controls the direction of the data port (BP43 or SD). Once started, the 8 data bits are,

depending on the selected direction, either clocked into or out of the shift register. Dur-

ing the 9th clock period, the port direction is automatically switched over so that the

corresponding acknowledge bit can be shifted out or read in. In transmit mode, the

acknowledge bit received from the device is captured in the SSI Status Register (TACK)

where it can be read by the controller. In receive mode, the state of the acknowledge bit

to be returned to the device is predetermined by the SSI Status Register (RACK).

76 5 432 1

765 4 3 21 0 7 6 5 4 3 21

msb

lsb

tx data 1

tx data 2

tx data 3

msb

lsb msb

lsb

Write STB

(tx data 2)

Write STB

(tx data 3)

Write STB

(tx data 1)

SIR

SRDY

Interrupt

(IFN = 0)

Interrupt

(IFN = 1)

ACT

4 32 1 0

7 6 54 32 1 0

msb

lsb

rx data 1

rx data 2

rx data 3

msb

lsb

msb

lsb

Read SRB

(rx data 2)

Read SRB

(rx data 3)

Read SRB

(rx data 1)

SIR

SRDY

Interrupt

(IFN = 0)

Interrupt

(IFN = 1)

ACT

76 5

43 2 1

76 5

76 5 4

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