PCA9541APWSLASH01 datasheet(9/45 Pages) NXP

9 / 45 page

PCA9541A

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Product data sheet

Rev. 5 — 24 April 2014

9 of 45

NXP Semiconductors

PCA9541A

2-to-1 I2C-bus master selector with interrupt logic and reset

2. A built-in bus initialization/recovery function can take temporary control of the

downstream channel to initialize the bus before making the actual switch to the new

bus master. This function is activated by setting the BUSINIT to logic 1 by the master

during the same write sequence as the one programming MYBUS and BUSON bits.

When activated and whether the bus was previously idle or not:

a. 9 clock pulses are sent on the SCL_SLAVE.

b. SDA_SLAVE line is released (HIGH) when the clock pulses are sent to

SCL_SLAVE. This is equivalent to sending 8 data bits and a not acknowledge.

c. Finally a STOP condition is sent to the downstream slave channel.

This sequence completes any read transaction which was previously in process and

the downstream slave configured as a slave-transmitter should release the SDA line

because the PCA9541A did not acknowledge the last byte.

3. When the initialization has been requested and completed, the PCA9541A sends an

interrupt to the new master through its INT line and connects the new master to the

downstream channel. BUSINIT bit in the Interrupt Status Register is set. The switch

operation occurs after the master asking the bus control has sent a STOP

command. This interrupt can be masked by setting the BUSINITMSK bit to logic 1.

4. When the bus initialization/recovery function has not been requested (BUSINIT = 0),

the PCA9541A connects the new master to the slave downstream channel. The

switch operation occurs after the master asking the bus control has sent a

STOP command. If the built-in bus sensor function detects a non-idle condition in the

downstream slave channel at the switching time, PCA9541A sends an interrupt to the

new master through its INT line. BUSOK bit in the Interrupt Status Register is set. This

means that a STOP condition has not been detected in the previous bus

communication and that an external bus recovery/initialization must be performed. If

an idle condition has been detected at the switching time, no interrupt is sent. This

interrupt can be masked by setting the BUSOKMSK bit to logic 1.

Interrupt status can be read. See Section 7.4 “Interrupt Status registers” for more

information.

The MYTEST and the NMYTEST bits cause the interrupt pins of the respective masters to

be activated for a ‘functional interrupt test’.

Remark: The regular way to proceed is that a master asks to take the control of the bus

by programming MYBUS and BUSON bits based on NMUYBUS and NBUSON values.

Nevertheless, the same master can also decide to give up the control of the bus and give

it to the other master. This is also done by programming the MYBUS and BUSON bits

based on NMYBUS and NBUSON values.

Remark: Any writes either to the Interrupt Enable Register or the Control Register cause

the respective register to be updated on the ninth clock cycle, that is, on the rising edge of

the acknowledge clock cycle.

Remark: The actual switch from one channel to another or the switching off of both the

channels happens on a STOP command that is sent by the master requesting the switch.

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