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PCA9541AD/01 датащи(PDF) 6 Page - NXP Semiconductors |
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PCA9541AD/01 датащи(HTML) 6 Page - NXP Semiconductors |
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6 / 45 page ![]() PCA9541A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 24 April 2014 6 of 45 NXP Semiconductors PCA9541A 2-to-1 I2C-bus master selector with interrupt logic and reset 6.2 Pin description [1] HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad must be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias must be incorporated in the printed-circuit board in the thermal pad region. 7. Functional description Refer to Figure 1 “Block diagram of PCA9541A”. 7.1 Device address Following a START condition, the upstream master that wants to control the I2C-bus or make a status check must send the address of the slave it is accessing. The slave address of the PCA9541A is shown in Figure 5. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable pins and they must be pulled HIGH or LOW. Table 3. Pin description Symbol Pin Description SO16, TSSOP16 HVQFN16 INT0 1 15 active LOW interrupt output 0 (external pull-up required) SDA_MST0 2 16 serial data master 0 (external pull-up required) SCL_MST0 3 1 serial clock master 0 (external pull-up required) RESET 4 2 active LOW reset input (external pull-up required) SCL_MST1 5 3 serial clock master 1 (external pull-up required) SDA_MST1 6 4 serial data master 1 (external pull-up required) INT1 7 5 active LOW interrupt output 1 (external pull-up required) VSS 86[1] supply ground A0 9 7 address input 0 (externally held to VSS or VDD) A1 10 8 address input 1 (externally held to VSS or VDD) A2 11 9 address input 2 (externally held to VSS or VDD) A3 12 10 address input 3 (externally held to VSS or VDD) SCL_SLAVE 13 11 serial clock slave (external pull-up required) SDA_SLAVE 14 12 serial data slave (external pull-up required) INT_IN 15 13 active LOW interrupt input (external pull-up required) VDD 16 14 supply voltage Fig 5. Slave address 002aab390 1 1 1 A3 A2 A1 A0 R/W fixed hardware selectable |
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