SML2120

30

2066 6.3 1/22/04

Summit Microelectronics

Configuration Register 15 - Address 0x10F

This register contains fast mode enable, alarm control, configuration lockout, and write protect information.

Bits

Default

Description

76

54321

0

0

0b0

Fast Mode on ENA# is disabled

1

Fast Mode on ENA# is enabled.

0

0b0

WP status bit

1

asserted.

0

0b0

Alarm reset. A write to the status register will reset Alarm.

1

Alarm reset. When the AM# pin is de-asserted, the Alarm is reset.

0

0b0

Alarm Forces Shutdown. When this bit is cleared, an alarm does not

cause a shutdown.

1

Alarm Forces Shutdown. When this bit is set, an alarm causes a

shutdown.

0

0b0

Configuration Lockout. When this bit is cleared, the configuration

registers are not locked out and can be accessed.

1

Configuration Lockout. When this bit is set, the configuration registers

are locked out and cannot be accessed.

0

0b0

Write-protect not set on power-up.

1

Write-protect set on power-up.

00

0b11

Sample interval is 0.4 ms.

0

1

Sample interval is 3.2 ms.

1

0

Sample interval is 51.2 ms.

1

1

Sample interval is 409.6 ms.

Table 21. Configuration Register 15 Bitmap