BLC9G22LS-160VT

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© Ampleon Netherlands B.V. 2017. All rights reserved.

Product data sheet

Rev. 2 — 24 May 2017

4 of 16

BLC9G22LS-160VT

Power LDMOS transistor

7.2 Impedance information

[1]

[2]

at 3 dB gain compression.

Table 8.

Typical impedance

f

(MHz)

(

)

(

)

(W)

(%)

(dB)

Maximum power load

2110

2.0

 j5.6

1.4

 j3.1

199.6

58.9

15.5

2140

2.3

 j5.9

1.3

 j3.0

198.0

58.3

15.5

2170

2.7

 j6.4

1.3

 j3.1

197.9

58.9

15.6

Maximum drain efficiency load

2110

2.0

 j5.6

2.6

 j1.9

135.6

67.5

17.9

2140

2.3

 j5.9

2.3

 j1.9

139.4

67.2

17.8

2170

2.7

 j6.4

2.3

 j1.8

132.5

67.4

18.1

Fig 1.

Definition of transistor impedance

001aaf059

drain

gate