ADSP-SC596 datasheet(91/134 Pages) AD

91 / 134 page

Rev. PrD

Page 91 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

SPI Port—SPIx_RDY Master Timing

SPIx_RDY is used to provide flow control. CPOL and CPHA are configuration bits in the SPIx_CTL register, whereas LEADX, LAGX,

and STOP are configuration bits in the SPIx_DLY register.

Table 55. SPI Port—SPIx_RDY Master Timing1

1 All specifications apply to all three SPIs.

All specifications are based on simulation data and are subject to change without notice.

Parameter

Conditions

Min

Max

Unit

Timing Requirement

tSRDYSCKM

Setup Time for SPIx_RDY

Deassertion Before Last Valid

Data SPIx_CLK Edge

(2 + 2 × BAUD2) × tCDU_CLKO6 + 11

2 BAUD value is set using the SPIx_CLK.BAUD bits. BAUD value = SPIx_CLK.BAUD bits + 1.

Switching Characteristic

tDRDYSCKM

3 Specification assumes the LEADX, LAGX, and STOP bits in the SPI_DLY register are zero.

Assertion of SPIx_RDY to First

SPIx_CLK Edge of Next Transfer

BAUD = 0, CPHA = 0 4.5 × tCDU_CLKO6

5.5 × tCDU_CLKO6 + 12

BAUD = 0, CPHA = 1 4 × tCDU_CLKO6

5 × tCDU_CLKO6 + 12

BAUD > 0, CPHA = 0 (1 + 1.5 × BAUD2) × tCDU_CLKO6

(2 + 2.5 × BAUD2) × tCDU_CLKO6 +12 ns

BAUD > 0, CPHA = 1 (1 + 1 × BAUD2) × tCDU_CLKO6

(2 + 2 × BAUD2) × tCDU_CLKO6 + 12 ns

Figure 25. SPIx_RDY Setup Before SPIx_CLK

SPIx_CLK

(CPOL = 0)

SPIx_CLK

(CPOL = 1)

tSRDYSCKM

SPIx_RDY

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