MDT10P721

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P. 21

2005/6 Ver. 2.0

10.Block Diagram

S ta ck 8 Le ve ls

P ro g ra m C o u n te rs

O s cilla to r Circu it

P o we r o n R e s e t

P o we r Do w n Re s e t

C o u n te r / Tim e r0

E P R O M

4 Kx 1 4 (MD T1 0 P 7 2 1 )

In s tru ctio n

Re g is te r

In s tru ctio n

De co d e r

W o rkin g R e g is te r

ALU

S e ria l P o rt

(S CM)

RAM

1 9 2 X8

S p e c ia l Re g is te r

Co n tro l C ircu it

S ta tu s R e g is te r

W DT/O S T

Tim e r

P o rt A

P o rt B

O S C1

O S C2 MC LR

D a ta 8 -b it

1 4 b its

P ortA

P A0 ~P A5

6 b its

D0 ~ D7

P o rtC

P o rtC

P C0 ~P C 7

8 bits

P ortB

P B0 ~P B7

8 b its

A/D 8 b it

Tim e r1 / Tim e r2

(C CP 1 )

P o we r R a ng e Detecto r

1 2 b its

1 2 b its