NBP8 datasheet(8/58 Pages) NXP

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NXP Semiconductors

NBP8

Battery pressure monitor sensor

6.2 Serial peripheral interface (SPI) module

The SPI module is configured as a standard client SPI which allows a full duplex,

synchronous, serial communication between the unit and a server SPI device.

The principal features of the SPI block are summarized as follows:

• Client only mode operation.

• Full-duplex, 4 wire, synchronous serial communication.

• Command-Response communication format.

• SCLK operation up to 10 MHz supported.

• Fixed Clock polarity and phase supported (CPOL=0, CPHA = 0).

– The SPI module requires the base clock value to be at the low state (CPOL = 0) with

data captured on the rising edge of the clock and data propagated on the falling edge

of the clock (CPHA = 0).

• Supports 8-bit register read and write operations via 16 clock transfers.

• Even Parity error-checking.

• Alternate bus controller for the system-on-chip (SoC) internal IP Bus system.

– SPI can be used to access the entire Memory map of the NBP8.

• Contains eight, 8-bit memory mapped registers for user and test mode operations.

• Decodes SPI test mode entry sequence and enables SPI test mode.

As a client, the SPI interface is compatible with SPI interface mode 00, corresponding

to CPOL = 0 and CPHA = 0. For CPOL = 0, the idle value of the clock is zero, and the

active value of the clock is 1. For CPHA = 0, data is captured on the rising edge (low

to high transition) of the clock and data is propagated on the falling edge (high to low

transition) of the clock.

As a client, the CS_B pin is driven low at the start of a transaction, held low for the

duration of the transfer, and then driven high again after the transaction is completed.

During a transaction, the server toggles the clock (SCLK). The SCLK polarity is defined

as having an idle value that is low, and an active phase that is high (CPOL = 0). Serial

input and output data is captured on the rising edge of the colock and propagated on the

falling edge (CPHA = 0). Single-byte read and single-byte write operations are completed

in two strobes of CS_B of 16 SCLK cycles each; multiple byte reads and writes are

completed in additional multiples of 16 SCLK cycles. The first SCLK cycle latches the

most significant bit on SOCI to select whether the desired operation is a read (R/W = 1)

or a write (R/W = 0). The following 13 SCLK cycles are used to latch the client register

read or write address. The final two SCLK cycles are used to latch the parity calculation

results.

When memory is secured by SEC[1:0] settings, the SPI may access only the address

ranges indicated in Section 6.8 "Read/write targets accessible by the external host via

SPI". Other access attempts result in an error status as defined below.

Note: The SPI and the CPU share the internal address, data, and control bus, and

are arbitrated such that the SPI takes priority over the CPU. The user application must

account for inhibited execution of CPU instructions during the time the SPI has taken

control of the internal bus.

NBP8

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.4 — 11 March 2022

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