SiP12117

www.vishay.com

Vishay Siliconix

S20-0484-Rev. C, 29-Jun-2020

9

Document Number: 62973

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

OPERATIONAL DESCRIPTION

Device Overview

SiP12117 is a high efficiency monolithic synchronous buck

regulator capable of delivering up to 3 A continuous

current. The device has fixed switching frequency of

600 kHz. The control scheme is based on current - mode

constant-on-time architecture, which delivers fast transient

response and minimizes external components. Thanks to

the internal current ramp information, no high ESR output

bulk or virtual ESR network is required for the loop stability.

SiP12117 has a full set of protection features:

• Cycle by cycle over current protection

• Over temperature protection with hysteresis

The device also features a dedicated enable pin for easy

power sequencing and an open drain power good output.

The device is available in 3 x 3 DFN10 package with an

exposed power pad to deliver high power density with ease

of use.

Power Stage

SiP12117 integrates a high performance power stage with

an 85 m

 n-channel high side MOSFET and a 55 m

n-channel low side MOSFET. The MOSFETs are optimized

to achieve up to 95 % efficiency at 600 kHz switching

frequency.

as low as 4.5 V for power conversion.

PWM Control Mechanism

SiP12117 employs a state-of-the-art current - mode COT

(CM-COT)

control

mechanism.

During

steady-state

operation, output voltage is compared with internal

generated. In the meantime, inductor valley current is

Light Load Operation

To further improve efficiency at light-load condition,

SiP12117 provides a set of innovative implementations to

eliminate LS recirculating current and switching losses. The

internal Zero Crossing Detector (ZCD) monitors LX node

voltage to determine when inductor current starts to flow

negatively. In light load operation as soon as inductor valley

current crosses zero, the device first deploys diode

emulation mode by turning off LS FET. If load further

decreases,

switching

frequency

is

further

reduced

proportional to load condition to save switching losses while

keeping output ripple within tolerance. The switching

frequency is set by the control loop to maintain regulation.

At zero load this frequency can go as low as hundreds of Hz.

Fig. 19 illustrates the basic block diagram for CM-COT

architecture and fig. 20 demonstrates the basic operational

principle:

Fig. 19 - CM-COT Block Diagram

Fig. 20 - CM-COT Operational Principle

HG

LG

HG

LG

OTA

-

+

Bandgap

Current

mirror

LS FET

PWM

comperator

-

+

-

+

I-AMP

On-time

generator

Control

logic &

MOSFET

driver

I

sense

V

current

V

comp

PWM

Fixed on-time