ADP5310 datasheet(24/28 Pages) AD

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ADP5310

Data Sheet

Rev. A | Page 24 of 28

CAPACITOR SELECTION

Output Capacitor

TheADP5310 is designed for operation with small, space-saving

ceramic capacitors, but functions with most common capacitors

provided that the ESR value is carefully considered. The ESR of

the output capacitor affects the stability of the control loop. A

minimum output capacitance of 6.2 µF with an ESR of 10 mΩ

or less is recommended to ensure the stability of the ADP5310.

Input Bypass Capacitor

Connect a 10 µF capacitor from PVINx to PGND to reduce the

circuit sensitivity to the printed circuit board (PCB) layout,

especially when long input traces or high source impedance are

encountered. If greater than 10 µF of output capacitance is

required, increase the input capacitor to match the output

capacitance to improve the transient response.

Input and Output Capacitor Properties

Use any good quality ceramic capacitors with the ADP5310;

however they must meet the minimum capacitance and

maximum ESR requirements. Ceramic capacitors are manu-

factured with a variety of dielectrics, each with different behavior

over temperature and applied voltage. Capacitors must have a

dielectric adequate to ensure the minimum capacitance over the

necessary temperature range and dc bias conditions. X5R or X7R

dielectric capacitors with a voltage rating of 6.3 V to 25 V are

recommended for best performance. Y5V and Z5U dielectrics

are not recommended because of their poor temperature and dc

bias characteristics.

Use the following equation to determine the worst-case

capacitance, accounting for capacitor variation over

temperature, component tolerance, and voltage:

CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)

where:

CBIAS is the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient (TC).

TOL is the worst-case component tolerance.

In this example, the worst-case TC over −40°C to +85°C is

assumed to be 15% for an X5R dielectric. The tolerance of the

capacitor (TOL) is assumed to be 10%, and CBIAS is 8.53 μF at 12 V

for the 10 μF, 35 V capacitor in a 1210 package.

Substituting these values in Equation 1 yields

CEFF = 8.53 μF × (1 − 0.15) × (1 − 0.1) = 6.53 μF

Therefore, the capacitor chosen in this example meets the

minimum capacitance requirement of the ADP5310 over

temperature and tolerance at the chosen output voltage.

To guarantee the performance of the ADP5310, it is imperative

that the effects of dc bias, temperature, and tolerances of the

capacitors are evaluated for each application.

CIRCUIT BOARD LAYOUT RECOMMENDATIONS

15.75

8.94

AGND

12 PWRGD

13 FB1

14 EN1

15 PGND1

16 SW1

11 SYNC/MODE

10 VREG

4.7µH

4mm × 4mm

4.7µH

4mm × 4mm

10µF

25V/X5R

1206

10µF

25V/X5R

1206

100k

0402

ADP5310

1.0µF

6.3V/X5R

0603

10µF

25V/X5R

1206

PVIN2

SW2

PGND2

FB2

PVIN1

EN3

VOUT3

Figure 57. Typical PCB Layout for the ADP5310

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