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ADP1850ACPZ-R7 датащи(PDF) 31 Page - Analog Devices |
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ADP1850ACPZ-R7 датащи(HTML) 31 Page - Analog Devices |
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31 / 32 page ![]() Data Sheet ADP1850 Rev. C | Page 31 of 32 OUTLINE DIMENSIONS 0.50 0.40 0.30 1 0.50 BSC BOTTOM VIEW TOP VIEW TOP VIEW PIN 1 INDICATOR 32 9 16 17 24 25 8 EXPOSED PAD SEATING PLANE 0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08 0.30 0.25 0.18 5.10 5.00 SQ 4.90 0.80 0.75 0.70 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.25 MIN 3.75 3.60 SQ 3.55 COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5. PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) DETAIL A (JEDEC 95) Figure 48. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body and 0.75 mm Package Height (CP-32-12) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADP1850ACPZ-R7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-12 ADP1850SP-EVALZ Evaluation Board in Single-Phase Mode with 14 A Output ADP1850DP-EVALZ Evaluation Board in Dual-Phase Mode with 50 A Output 1 Z = RoHS Compliant Part. |
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