ADN8810

Data Sheet

Rev. C | Page 10 of 14

FUNCTIONAL DESCRIPTION

The ADN8810 is a single 12-bit current output digital-to-analog

converter (DAC) with a 3-wire SPI interface. Up to eight devices

can be independently programmed from the same SPI bus.

The full-scale output current is set with two external resistors.

The maximum output current can reach 300 mA. Figure 17

shows the functional block diagram of the ADN8810.

DVDD

SB

CS

VREF

BIAS

GEN

SCLK

SDI

PVDD

PVDD

IOUT

IOUT

AVSS

AVDD

DGND

ADDR2 ADDR1 ADDR0

DVSS

RESET

15kΩ

1.5kΩ

FAULT

FAULT

DETECTION

12-BIT

DATA LATCH

ADDRESS

DECODER

12-BIT

DAC

CONTROL

LOGIC

RSN

1.5kΩ

FB

ENCOMP

Figure 17. Functional Blocks, Pins, and Internal Connections

SETTING FULL-SCALE OUTPUT CURRENT

Two external resistors set the full-scale output current from the

in Figure 1. Use 1% or better tolerance resistors to achieve the

most accurate output current and the highest output

impedance.

Equation 3 shows the approximate full-scale output current.

The exact output current is determined by the data register code

as shown in Equation 4. The variable code is an integer from 0

to 4095, representing the full 12-bit range of the ADN8810.

SN

FS

R

I

×

≈

10

096

.

4

(3)

















+

Ω

×

×

=

1

.

0

15

1

000

,1

k

R

R

Code

I

SN

SN

OUT

(4)

The ADN8810 is designed to operate with a 4.096 V reference

voltage connected to VREF. The output current is directly

proportional to this reference voltage. To achieve the best

performance, use a low noise precision (the ADR292, ADR392,

or REF198 is recommended).

POWER SUPPLIES

There are three principal supply current paths through the

ADN8810:

•

AVDD provides power to the analog front end of the

ADN8810 including the DAC. Use this supply line to

power the external voltage reference. For best performance,

AVDD must be low noise.

•

DVDD provides power for the digital circuitry. This

includes the serial interface logic, the SB and RESET logic

inputs, and the FAULT output. Tie DVDD to the same

supply line used for other digital circuitry. It is not

necessary for DVDD to be low noise.

•

PVDD is the power pin for the output amplifier. It can

operate from as low as 3.0 V to minimize power dissipation

in the ADN8810. For best performance, PVDD must be

low noise.

Current is returned through the following three pins:

•

AVSS is the return path for both AVDD and PVDD. This

pin is connected to the substrate of the die as well as the

slug on the bottom of the lead frame chip scale package

(LFCSP). For single-supply operation, connect this pin to a

low noise ground plane.

•

DVSS returns current from the digital circuitry powered by

DVDD. Connect DVSS to the same ground line or plane

used for other digital devices in the application.

•

DGND is the ground reference for the digital circuitry. In a

single-supply application, connect DGND to DVSS.

For single-supply operation, set AVDD to 5 V, set PVDD from

3.0 V to 5 V, and connect AVSS, AGND, and DGND to ground.

SERIAL DATA INTERFACE

The ADN8810 uses a serial peripheral interface (SPI) with three

input signals: SDI, CLK, and CS. Figure 2 shows the timing

diagram for these signals.

Data applied to the SDI pin is clocked into the input shift

register on the rising edge of CLK. After all 16 bits of the data-

word have been clocked into the input shift register, a logic high

on CS loads the shift register byte into the ADN8810. If more

than 16 bits of data are clocked into the shift register before CS

goes high, bits are pushed out of the register in first-in first-out

(FIFO) fashion.

The four MSB of the data byte are checked against the address

of the device. If they match, the next 12 bits of the data byte are

loaded into the DAC to set the output current. The first bit

(MSB) of the data byte must be a logic zero, and the following

three bits must correspond to the logic levels on pins ADDR2,

ADDR1, and ADDR0, respectively, for the DAC to be updated.

Up to eight ADN8810 devices with unique addresses can be

driven from the same serial data bus.

Table 5 shows how the 16-bit DATA input word is divided into

an address byte and a data byte. The first four bits in the input

word correspond to the address. Note that the first bit loaded

(A3) must always be zero. The remaining bits set the 12-bit data

byte for the DAC output. Three example inputs are demonstrated.