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ADL5390 датащи(PDF) 13 Page - Analog Devices

номер детали ADL5390
подробное описание детали  RF/IF Vector Multiplier
PDF  23 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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ADL5390 датащи(HTML) 13 Page - Analog Devices

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Data Sheet
ADL5390
Rev. A | Page 13 of 23
RF OUTPUT AND MATCHING
The RF/IF outputs of the ADL5390, RFOP and RFOM, are open
collectors of a transimpedance amplifier that need to be pulled
up to the positive supply, preferably with RF chokes, as shown
in Figure 30. The nominal output impedance looking into each
individual output pin is 25 Ω. Consequently, the differential
output impedance is 50 Ω.
50
DIFFERENTIAL
10pF
1:1
RF
OUTPUT
RFOM
RFOP
RT
RT
120nH
10pF
VP
GM
±ISIG
0.1
F
Figure 30. RF Output Interface to the ADL5390 Showing
Coupling Capacitors, Pull-Up RF Chokes, and Balun
Since the output dc levels are at the positive supply, ac-coupling
capacitors are usually needed between the ADL5390 outputs
and the next stage in the system.
A 1:1 RF broadband output balun, such as the ETC1-1-13
(M/A-COM), converts the differential output of the ADL5390
into a single-ended signal. Note that the loss and balance of the
balun directly impact the apparent output power, noise floor, and
gain/phase errors of the ADL5390. In critical applications, narrow-
band baluns with low loss and superior balance are recommended.
If the output is taken in a single-ended fashion directly into a 50 Ω
load through a coupling capacitor, there will be an impedance
mismatch. This can be resolved with a 1:2 balun to convert the
single-ended 25 Ω output impedance to 50 Ω. If loss of signal
swing is not critical, a 25 Ω back termination in series with the
output pin can also be used. The unused output pin must still be
pulled up to the positive supply. The user may load it through a
coupling capacitor with a dummy load to preserve balance. The
mismatched gain of the ADL5390 when the output is single-ended
varies slightly with dummy load value, as shown in Figure 31.
10
–10
–4
–2
0
2
4
6
8
10
100
1000
10000
FREQUENCY (MHz)
RL2 = OPEN
RL2 = 50
RL2 = SHORT
RL = 50
Figure 31. Gain of the ADL5390 Using a Single-Ended Output with Different
Dummy Loads, RL2 on the Unused Output, Gain Setpoint = 1.0
The RF output signal can be disabled by raising the DSOP pin
to the positive supply. The output disable function provides
>40 dB attenuation of the input signal, even at full gain. The
interface to DSOP is high impedance and the output disable
and output enable response times are <100 ns. If the output
disable function is not needed, the DSOP should be tied to
ground.
DRIVING THE I-Q BASEBAND GAIN CONTROLS
The I and Q gain control inputs to the ADL5390 set the gain for
each channel. These inputs are differential and should normally
have a common-mode level of 0.5 V. However, when differentially
driven, the common mode can vary from 250 mV to 750 mV
while still allowing full gain control. Each input pair has a
nominal input swing of ±0.5 V differential around the
common-mode level. The maximum gain is achieved if the
differential voltage is equal to +500 mV or −500 mV. So with a
common-mode level of 500 mV, IBBP and IBBM will each
swing between 250 mV and 750 mV.
The I and Q gain control inputs can also be driven with a single-
ended signal. In this case, one side of each input should be tied
to a low noise 0.5 V voltage source (a 0.1 μF decoupling
capacitor located close to the pin is recommended), while the
other input swings from 0 V to 1 V. Low speed, single-ended
drive can easily be achieved using 12-bit voltage output DACs
such as AD8303 (serial SPI® interface) or AD8582 (parallel
interface) DACs. A reference voltage should also be supplied.
Differential drive generally offers superior even-order distortion
and lower noise than single-ended drive.
The bandwidth of the baseband controls exceeds 200 MHz even at
full-scale baseband drive. This allows for very fast gain modulation
of the RF input signal. In cases where lower modulation band-
widths are acceptable or desired, external filter capacitors can
be connected across Pins IFLP to IFLM and Pins QFLP to
QFLM to reduce the ingress of baseband noise and spurious
signal into the control path.



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