PPC5604BACLL4R datasheet(59/109 Pages) NXP

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Package pinouts and signal descriptions

MPC5604B/C Microcontroller Data Sheet, Rev. 15

NXP Semiconductors

2.19

Flash memory electrical characteristics

2.19.1

Program/Erase characteristics

Table 28 shows the program and erase characteristics.

5 Only for the “P” classification: Data and Code Flash in Normal Power. Code fetched from RAM: Serial IPs CAN and

LIN in loop back mode, DSPI as Master, PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and

running at max frequency, periodic SW/WDG timer reset enabled.

6 Data Flash Power Down. Code Flash in Low Power. SIRC (128 kHz) and FIRC (16 MHz) on. 10 MHz XTAL clock.

FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clock gated. LINFlex:

instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 clock gated. eMIOS: instance: 0 ON (16

channels on PA[0]–PA[11] and PC[12]–PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked

but no communication). RTC/API ON. PIT ON. STM ON. ADC ON but not conversion except 2 analog watchdog.

7 Only for the “P” classification: No clock, FIRC (16 MHz) off, SIRC (128 kHz) on, PLL off, HPvreg off,

ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode.

8 When going from RUN to STOP mode and the core consumption is > 6 mA, it is normal operation for the main

regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction

temperatures exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the

maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to

the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA.

9 Only for the “P” classification: ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum

consumption, all possible modules switched off.

10 ULPreg on, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules

switched off.

Table 28. Program and erase specifications

Symbol

Parameter

Value

Unit

Min

Typ1

1 Typical program and erase times assume nominal supply values and operation at 25 °C.

Initial

max2

2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.

Max3

3 The maximum program and erase times occur after the specified number of program/erase cycles. These maximum

values are characterized but not guaranteed.

Tdwprogram CC C Double word (64 bits) program time

4 Actual hardware programming times. This does not include software overhead.

—22

500

µs

T16Kpperase

16 KB block preprogram and erase time

—

300

500

5000

T32Kpperase

32 KB block preprogram and erase time

—

400

600

5000

T128Kpperase

128 KB block preprogram and erase time

—

800

1300

7500

Tesus

CC D Erase suspend latency

—

µs

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