MM54HC181 datasheet(2/10 Pages) NSC

2 / 10 page

General Description (Continued)

These circuits will accommodate active-high or active-low

data if the pin designations are interpreted as shown below

Subtraction is accomplished by 1’s complement addition

where the 1’s complement of the subtrahend is generated

internally The resultant output is AB1 which requires

an end-around or forced carry to produce AB

The 181 can also be utilized as a comparator The AeB

output is internally decoded from the function outputs (F0

F1 F2 F3) so that when two words of equal magnitude are

applied at the A and B inputs it will assume a high level to

indicate equality (AeB) The ALU should be in the subtract

mode with CneH when performing this comparison The

AeB output is open-drain so that it can be wire-AND con-

nected to give a comparison for more than four bits The

carry output (Cna4) can also be used to supply relative

magnitude information Again the ALU should be placed in

the subtract mode by placing the function select inputs S3

S2 S1 S0 at L H H L respectively

These circuits have been designed to not only incorporate

all of the designer’s requirements for arithmetic operations

but also to provide 16 possible functions of two Boolean

variables without the use of external circuitry These logic

functions are selected by use of the four function-select in-

puts (S0 S1 S2 S3) with the mode-control input (M) at a

high level to disable the internal carry The 16 logic func-

tions are detailed in Tables 1 and 2 and include exclusive-

OR NAND AND NOR and OR functions

ALU SIGNAL DESIGNATIONS

The MM54HC181MM74HC181 can be used with the signal

designations of either

Figure 1 or Figure 2

The logic functions and arithmetic operations obtained with

signal designations as in

Figure 1 are given in Table 1 those

obtained with the signal designations of

Figure 2 are given

in Table 2

The 54HC74HC logic family is speed function and pinout

compatible with the standard 54LS74LS logic family All

inputs are protected from damage due to static discharge by

internal diode clamps to VCC and ground

Pin Number

Active-High Data (Table 1)

Cna4

Active-Low Data (Table 1)

A0B0A1B1A2B2A3B3F0F1F2F3Cn

Cna4

Input

Output

Active-High Data

Active-Low Data

Cna4

(Figure 1)

(Figure 2)

AsBAtB

AlBAkB

AkBAlB

AtBAsB

TLF5320 – 2

FIGURE 1

Table I

Selection

Active High Data

MeHMeL Arithmetic Operations

Logic

S3 S2 S1 S0 Functions

CneH (no carry)

CneL (with carry)

LLLL FeA

FeAFeA Plus 1

LLL

H FeA a B FeA a BFe(A a B) Plus 1

L FeABFeA a B

Fe(A a B) Plus 1

H Fe0FeMinus 1 (2’s Compl) FeZero

LHL

L FeAB

FeA Plus AB

FeA Plus AB Plus 1

LHLH FeB

Fe(A a B) Plus AB

Fe(A a B) Plus AB Plus 1

HL FeA Z BFeA Minus B Minus 1

FeA Minus B

H FeAB

FeAB Minus 1

FeAB

L FeA a BFeA Plus AB

FeA Plus AB Plus 1

LH FeA Z B FeA Plus B

FeA Plus B Plus 1

HLHL FeBFe(A a B) Plus AB

Fe(A a B) Plus AB Plus 1

HLH

H FeAB

FeAB Minus 1

FeAB

L Fe1FeA Plus A

FeA Plus A Plus 1

H FeA a B Fe(A a B) Plus A

Fe(A a B) Plus A Plus 1

HHH

L FeA a BFe(A a B) Plus A

Fe(A a B) Plus A Plus 1

HHHH FeAFeA Minus 1

FeA

Each bit is shifted to the next more significant position

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