AD5753 datasheet(40/75 Pages) AD

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ADFS5758

Data Sheet

Rev. 0 | Page 40 of 75

The 16-bit USER_OFFSET register allows the user to adjust the

offset of the DAC channel by −32,768 LSBs to +32,768 LSBs in

steps of 1 LSB. The USER_OFFSET register coding is straight

binary as shown in Table 15. The default code in the USER_

OFFSET register is 0x8000, which results in zero offset

programmed to the output.

Table 15. Offset Register Adjustment

Gain Adjustment

D15

D13 to D2

+32,768 LSBs

+32,767 LSBs

…

No Adjustment (Default)

…

−32,767 LSBs

−32,768 LSBs

The value (in decimal) that is written to the internal DAC

)

(

−

Code

DAC

(1)

where:

D is the code loaded to the DAC_INPUT register.

M is the code in the USER_GAIN register (default code = 216 − 1).

C is the code in the USER_OFFSET register (default code = 215).

Data from the DAC_INPUT register is processed by a digital

multiplier and adder, controlled by the contents of the user

gain and USER_OFFSET registers, respectively. The calibrated

DAC data is then loaded to the DAC, dependent on the state of

the LDAC pin.

Each time data is written to the USER_GAIN or USER_

OFFSET register, the DAC output is not automatically updated.

Instead, the next write to the DAC_INPUT register uses these

user gain and user offset values to perform a new calibration

and automatically updates the channel. The read only

DAC_OUTPUT register represents the value currently

available at the DAC output except in the case of user gain and

user offset calibration. In this case, the DAC_OUTPUT register

represents the DAC data input by the user, on which the

calibration was performed and not the result of the calibration.

Both the USER_GAIN register and the USER_OFFSET register

have 16 bits of resolution. The correct method to calibrate the

gain and offset is to first calibrate the gain and then calibrate

the offset.

DAC OUTPUT UPDATE AND DATA INTEGRITY

DIAGNOSTICS

Figure 83 shows a simplified version of the DAC input loading

circuitry. If used, the USER_GAIN and USER_OFFSET

registers must be updated before writing to the DAC_INPUT

The DAC_OUTPUT register (and ultimately the DAC output)

updates in any of the following cases:

•

If a write is performed to the DAC_INPUT register with

the hardware LDAC pin tied low, the DAC_OUTPUT

the timing specifications in Table 2.

•

If the hardware LDAC pin is high and a write to the

DAC_INPUT register occurs, the DAC_OUTPUT register

does not update until a software LDAC instruction is

issued or the hardware LDAC pin is pulsed low.

•

If a WDT timeout occurs with the CLEAR_ON_WDT_FAIL

bit set, the CLEAR_CODE register contents are loaded to

the DAC_OUTPUT register.

•

If the slew rate control feature is enabled, the

DAC_OUTPUT register contains the dynamic value of the

DAC as it slews between values.

Note that, while a WDT fault is active, all writes to the DAC_

INPUT register as well as hardware or software LDAC events

are ignored. If the CLEAR_ON_WDT_FAIL bit was set, such

that the output was set to the clear code, when the WDT fault

flag is cleared, the DAC_INPUT register must be written to

before an update to the DAC_OUTPUT register occurs, that is,

performing a software or hardware LDAC only reloads the DAC

with the clear code. As described in the Echo Mode section, after

configuring the DAC range (via the DAC_CONFIG register), a

write to the DAC_INPUT register must occur, even if the contents

of the DAC_INPUT register are not changing from their current

value.

Note also that the GP_CONFIG2 register contains a bit to enable a

global software LDAC mode, whereby the ADFS5758 address

bits of the SW_LDAC command are ignored, thus enabling

multiple ADFS5758 devices to be simultaneously updated using

a single SW_LDAC command. This is a useful feature if the

hardware LDAC pin is not being used in a system containing

multiple ADFS5758 devices.

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